參數(shù)資料
型號: R1Q2A3609BBG-50RB
元件分類: SRAM
英文描述: 4M X 9 QDR SRAM, PBGA165
封裝: 15 X 17 MM, 1 MM PITCH, LEAD FREE, PLASTIC, LBGA-165
文件頁數(shù): 25/26頁
文件大?。?/td> 341K
代理商: R1Q2A3609BBG-50RB
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 8 of 24
2b. Sequence controlled by Clock (/DOFF pin fixed high) when DLL enable
Status
Power Up
Unstable
Clock Stage
Stop
Clock Stage
NOP & DLL
Locking Stage
Normal
Operation
VDD
C, /C, K, /K
30ns min.
1024cycle min.
VDDQ
VREF
/DOFF
DLL Constraints
1. DLL uses either K or C clock as its synchronizing input, the input should have low phase jitter which is specified as
TKC var.
2. The lower end of the frequency at which the DLL can operate is 119MHz.
Programmable Output Impedance
1. Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor (RQ).
The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance
matching with a tolerance of 10% is 250
typical.
The total external capacitance of ZQ ball must be less than 7.5 pF.
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