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參數(shù)資料
| 型號： | R1Q2A3609BBG-50RB |
| 元件分類： | SRAM |
| 英文描述： | 4M X 9 QDR SRAM, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, LEAD FREE, PLASTIC, LBGA-165 |
| 文件頁數(shù)： | 2/26頁 |
| 文件大?。?/td> | 341K |
| 代理商： | R1Q2A3609BBG-50RB |
R1Q2A3636B/R1Q2A3618B/R1Q2A3609B
REJ03C0341-0003 Rev.0.03 Apr. 11, 2008
Page 10 of 24
Byte Write Truth Table (x36)
Operation
K
/K
/BW0
/BW1
/BW2
/BW3
Write D0 to D35
↑
L
↑
L
Write D0 to D8
↑
L
H
↑
L
H
Write D9 to D17
↑
H
L
H
↑
H
L
H
Write D18 to D26
↑
H
L
H
↑
H
L
H
Write D27 to D35
↑
H
L
↑
H
L
Write nothing
↑
H
↑
H
Notes: 1. H: high level, L: low level,
↑: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
Byte Write Truth Table (x18)
Operation
K
/K
/BW0
/BW1
Write D0 to D17
↑
L
↑
L
Write D0 to D8
↑
L
H
↑
L
H
Write D9 to D17
↑
H
L
↑
H
L
Write nothing
↑
H
↑
H
Notes: 1. H: high level, L: low level,
↑: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
Byte Write Truth Table (x9)
Operation
K
/K
/BW
Write D0 to D8
↑
L
↑
L
Write nothing
↑
H
↑
H
Notes: 1. H: high level, L: low level,
↑: rising edge.
2. Assumes a WRITE cycle was initiated. /BWx can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| R1Q2A3609BBG-60R | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3609RBG-40RB0 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3609RBG-40RS0 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3609RBG-40RT0 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
| R1Q2A3609RBG-50RB0 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:36-Mbit QDR?II SRAM 2-word Burst |
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