參數(shù)資料
型號(hào)： QL8250
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
中文描述： 低功耗FPGA配合力性能密度和嵌入式內(nèi)存
文件頁(yè)數(shù)： 7/49頁(yè)
文件大?。?/td> 739K
代理商： QL8250
Preliminary
=
The modes for the ECU block are dynamically re-programmable through the programmable logic.
NOTE:
&&&
< 5
&56%%&&
$')*"-"
Instead of requiring extra components, designers simply need to instantiate one of the pre-
configured models (described in this section). The QuickLogic built-in PLLs support a wider range
of frequencies than many other PLLs. These PLLs also have the ability to support different ranges
of frequency multiplications or divisions, driving the device at a faster or slower rate than the
incoming clock frequency. When PLLs are cascaded, the clock signal must be routed off-chip
through the PLLPAD_OUT pin prior to routing into another PLL; internal routing cannot be used
for cascading PLLs.
PLLs achieve a very short clock-to-out time—generally less than 3 ns. This low clock-to-out time
is achieved by the PLL subtracting the clock tree delay through the feedback path, effectively
making the clock tree delay zero.
7%3,%
""
!'"
#(-"
./=2##
a. t
PD
, t
SU
and t
CO
do not include routing paths in/out of the ECU block.
b. Internal feedback path in ECU restricts max clk frequency to 238 MHz.
c. B [15:0] set to zero.
0
6
(
#!
0
0
0
Multiply
6.6 ns max
0
0
1
Multiply-Add
8.8 ns max
0
1
0
Accumulate
b
3.9 ns min
1.2 ns max
0
1
1
Add
3.1 ns max
1
0
0
Multiply (registered)
c
9.6 ns min
1.2 ns max
1
0
1
Multiply- Add (registered)
9.6 ns min
1.2 ns max
1
1
0
Multiply - Accumulate
9.6 ns min
1.2 ns max
1
1
1
Add (registered)
3.9 ns min
1.2 ns max
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QL8325 LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
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