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參數(shù)資料
| 型號： | QL8250 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| 中文描述： | 低功耗FPGA配合力性能密度和嵌入式內(nèi)存 |
| 文件頁數(shù)： | 11/49頁 |
| 文件大?。?/td> | 739K |
| 代理商： | QL8250 |
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Preliminary
(
)*
The bi-directional I/O pin options can be programmed for input, output, or bi-directional
operation. As shown in
=
, each bi-directional I/O pin is associated with an I/O cell which
features an input register, an input buffer, an output register, a three-state output buffer, an output
enable register, and 2 two-to-one multiplexers. The select lines of the two-to-one multiplexers are
static and must be connected to either Vcc or GND.
For input functions, I/O pins can provide combinatorial, registered data, or both options
simultaneously to the logic array. For combinatorial input operation, data is routed from I/O pins
through the input buffer to the array logic. For registered input operation, I/O pins drive the D
input of input cell registers, allowing data to be captured with fast set-up times without consuming
internal logic cell resources. The comparator and multiplexor in the input path allows for native
support of I/O standards with reference points offset from traditional ground.
For output functions, I/O pins can receive combinatorial or registered data from the logic array.
For combinatorial output operation, data is routed from the logic array through a multiplexer to
the I/O pin. For registered output operation, the array logic drives the D input of the output cell
register which in turn drives the I/O pin through a multiplexer. The multiplexer allows either a
combinatorial or a registered signal to be driven to the I/O pin. The addition of an output register
will also decrease the Tco. Since the output register does not need to drive the routing the length
of the output path is also reduced.
The three-state output buffer controls the flow of data from the array logic to the I/O pin and
allows the I/O pin to act as an input and/or output. The buffer's output enable can be individually
controlled by the logic cell array or any pin (through the regular routing resources), or it can be
bank-controlled through one of the global networks. The signal can also be either combinatorial
E
R
Q
D
R
Q
D
E
R
Q
D
+
-
PAD
OUTPUT ENABLE
REGISTER
OUTPUT
REGISTER
INPUT
REGISTER
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| QL8250-6PQN208C-5690 | 制造商:QuickLogic Corporation 功能描述: |
| QL8250-6PQN208C-5691 | 制造商:QuickLogic Corporation 功能描述: |
| QL82SD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| QL82SD-PB516 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| QL82SD-PQ208 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
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