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參數(shù)資料
| 型號(hào)： | QL8250 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| 中文描述： | 低功耗FPGA配合力性能密度和嵌入式內(nèi)存 |
| 文件頁數(shù)： | 10/49頁 |
| 文件大?。?/td> | 739K |
| 代理商： | QL8250 |
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Preliminary
4
!#
Eclipse-II features a variety of distinct I/O pins to maximize performance, functionality, and
flexibility with bi-directional I/O pins and input-only pins. All input and I/O pins are 1.8 V, 2.5 V,
and 3.3 V tolerant and comply with the specific I/O standard selected. For single ended I/O
standards, VCCIO specifies the input tolerance and the output drive. For voltage referenced I/O
standards (e.g SSTL), the voltage supplied to the INREF pins in each bank specifies the input
switch point. For example, the VCCIO pins must be tied to a 3.3 V supply to provide 3.3 V
compliance. Eclipse-II
can also support the LVDS and LVPECL I/O standards with the use of
external resistors ( see
< 3
).
As designs become more complex and requirements more stringent, several
application-specific I/O standards have emerged for specific applications. I/O standards for
processors, memories, and a variety of bus applications have become commonplace and a
requirement for many systems. In addition, I/O timing has become a greater issue with specific
requirements for setup, hold, clock to out, and switching times. Eclipse-II has addressed these new
system requirements and now includes a completely new I/O cell which consists of programmable
I/Os as well as a new cell structure consisting of three registers—Input, Output, and OE.
Eclipse-II offers banks of programmable I/Os that address many of the bus standards that are
popular today. As shown in
=
each bi-directional I/O pin is associated with an I/O cell
which features an input register, an input buffer, an output register, a three-state output buffer, an
output enable register, and 2 two-to-one output multiplexers.
!",&
&/&
!"
-"7
!'7
''"
LVTTL
n/a
3.3 V
General Purpose
LVCMOS25
n/a
2.5 V
General Purpose
LVCMOS18
n/a
1.8 V
General Purpose
PCI
n/a
3.3 V
PCI Bus Applications
GTL+
1
n/a
Backplane
SSTL3
1.5
3.3 V
SDRAM
SSTL2
1.25
2.5 V
SDRAM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| QL8325 | LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM |
| QL80FC-APB456C | Telecomm/Datacomm |
| QL80FC-APB456I | Telecomm/Datacomm |
| QL80FC-APQ208C | Telecomm/Datacomm |
| QL80FC-APQ208I | Telecomm/Datacomm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL8250-6PQN208C-5690 | 制造商:QuickLogic Corporation 功能描述: |
| QL8250-6PQN208C-5691 | 制造商:QuickLogic Corporation 功能描述: |
| QL82SD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| QL82SD-PB516 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
| QL82SD-PQ208 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10 High Speed Bus LVDS Serial Links bandwidth up to 5 Gbps |
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