參數(shù)資料
型號(hào): QL8250
廠商: Electronic Theatre Controls, Inc.
英文描述: LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM
中文描述: 低功耗FPGA配合力性能密度和嵌入式內(nèi)存
文件頁(yè)數(shù): 27/49頁(yè)
文件大?。?/td> 739K
代理商: QL8250
Preliminary
0=
!"23,1,
,#!3,1,
#5,
A</%,&'&&/&'&<&
+
7
#+""
<"
"
t
SRA
RA setup time to RCLK: time the READ ADDRESS must be stable before the active
edge of the READ CLOCK
0.686 ns
-
t
HRA
RA hold time to RCLK: time the READ ADDRESS must be stable after the active
edge of the READ CLOCK
0 ns
-
t
SRE
RE setup time to WCLK: time the READ ENABLE must be stable before the active
edge of the READ CLOCK
0.243 ns
-
t
HRE
RE hold time to WCLK: time the READ ENABLE must be stable after the active
edge of the READ CLOCK
0 ns
-
t
RCRD
RCLK to RD: time between the active READ CLOCK edge and the time when the
data is available at RD
-
4.38 ns
#+"
"<"
r
PDRD
RA to RD: time between when the READ ADDRESS is input and when the DATA
is output
-
2.06 ns
tSRA
tHRA
RCLK
RA
tSRE
tHRE
tRCRD
old data
new data
RE
RD
rPDRD
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