參數(shù)資料
型號(hào): PSD913F2
英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
中文描述: 在8片位微控制器可配置存儲(chǔ)系統(tǒng)(用于8位微控制器的可配置存儲(chǔ)器系統(tǒng))
文件頁(yè)數(shù): 77/94頁(yè)
文件大?。?/td> 477K
代理商: PSD913F2
Preliminary Information
PSD9XX Family
73
-15
-20
Turbo
Off
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
LVLX
t
AVLX
t
LXAX
t
AVQV
t
SLQV
ALE or AS Pulse Width
26
30
ns
Address Setup Time
(Note 3)
10
12
ns
Address Hold Time
(Note 3)
12
14
ns
Address Valid to Data Valid
(Note 3)
150
200
Add 20
ns
CS Valid to Data Valid
150
200
ns
RD to Data Valid 8-Bit Bus
(Note 5)
35
40
ns
t
RLQV
RD or PSEN to Data Valid 8-Bit Bus,
8031, 80251
(Note 2)
50
55
ns
t
RHQX
t
RLRH
t
RHQZ
t
EHEL
t
THEH
t
ELTL
RD Data Hold Time
(Note 1)
0
0
ns
RD Pulse Width
40
45
ns
RD to Data High-Z
(Note 1)
40
45
ns
E Pulse Width
45
52
ns
R/W Setup Time to Enable
18
20
ns
R/W Hold Time After Enable
0
0
ns
t
AVPV
Address Input Valid to
Address Output Delay
(Note 4)
35
40
ns
Read Timing
(3 V Versions)
Microcontroller Interface – PSD9XXFV AC/DC Parameters
(3 V Versions)
NOTES:
1. RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
2. RD and PSEN have the same timing for 8031.
3. Any input used to select an internal PSD9XX function.
4. In multiplexed mode latched address generated from ADIO delay to address output on any Port.
5. RD timing has the same timing as DS, LDS, and UDS signals.
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