參數(shù)資料
型號: PSD913F2
英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
中文描述: 在8片位微控制器可配置存儲系統(tǒng)(用于8位微控制器的可配置存儲器系統(tǒng))
文件頁數(shù): 12/94頁
文件大?。?/td> 477K
代理商: PSD913F2
PSD9XX Family
Preliminary Information
8
5.7 In-System Programming
Using the JTAG signals on Port C, the entire PSD9XX device can be programmed or
erased without the use of the microcontroller (ISP). The main Flash memory can also be
programmed in-system by the microcontroller executing the programming algorithms out of
the Secondary Flash memory, or SRAM (IAP). The Secondary Flash memory can be
programmed the same way by executing out of the main Flash memory. The PLD logic
or other PSD9XX configuration can be programmed through the JTAG port or a device
programmer. Table 4 indicates which programming methods can program different
functional blocks of the PSD9XX.
PSD9XX
Architectural
Overview
(cont.)
Device
Programmer
Functional Block
JTAG-ISP
IAP
Main Flash Memory
Yes
Yes
Yes
Secondary Flash Memory
Yes
Yes
Yes
PLD Array (DPLD and GPLD)
Yes
Yes
No
PSD Configuration
Yes
Yes
No
Table 4. Methods of Programming Different Functional Blocks of the PSD9XX
5.8 Power Management Unit
The Power Management Unit (PMU) in the PSD9XX gives the user control of the power
consumption on selected functional blocks based on system requirements. The PMU
includes an Automatic Power Down unit (APD) that will turn off device functions due to
microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce power
consumption.
The PSD9XX also has some bits that are configured at run-time by the MCU to reduce
power consumption of the PLD. The turbo bit in the PMMR0 register can be turned off and
the PLD will latch its outputs and go to sleep until the next transition on its inputs.
Additionally, bits in the PMMR2 register can be set by the MCU to block signals from
entering the PLD to reduce power consumption. See section 9.5.
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