參數(shù)資料
型號(hào)： PSD913F2
英文描述： Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
中文描述： 在8片位微控制器可配置存儲(chǔ)系統(tǒng)（用于8位微控制器的可配置存儲(chǔ)器系統(tǒng)）
文件頁數(shù)： 64/94頁
文件大?。?/td> 477K
代理商： PSD913F2
PSD9XX Family
Preliminary Information
60
Port C Pin
PC0
PC1
PC3
PC4
PC5
PC6
JTAG Signals
TMS
TCK
TSTAT
TERR
TDI
TDO
Description
Mode Select
Clock
Status
Error Flag
Serial Data In
Serial Data Out
Table 34. JTAG Port Signals
The
PSD9XX
Functional
Blocks
(cont.)
9.5.3.4 Reset of Flash Erase and Programming Cycles (PSD934F2 Only)
An external reset on the RESET pin will also reset the internal Flash memory state
machine. When the Flash is in programming or erase mode, the RESET pin will terminate
the programming or erase operation and return the Flash back to read mode in tNLNH-A
(minimum 25 μs) time.
9.6 Programming In-Circuit using the JTAG Interface
The JTAG interface on the PSD9XX can be enabled on Port C (see Table 34). All
memory (Flash and Secondary Flash Block), PLD logic, and PSD configuration bits may be
programmed through the JTAG interface. A blank part can be mounted on a printed circuit
board and programmed using JTAG.
The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional
signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and
erase operations.
*
SR_cod bit in the VM Register are always cleared to zero on power on or warm reset.
**
Port Configuration
MCU I/O
PLD Output
Power On Reset
Input Mode
Valid after internal
PSD configuration
bits are loaded
Tri-stated
Tri-stated
Warm Reset
Input Mode
Valid
Power Down Mode
Unchanged
Depend on inputs to
PLD (address are
blocked in PD mode)
Not defined
Tri-stated
Address Out
Data Port
Tri-stated
Tri-stated
Table 33. Status During Power On Reset, Warm Reset and Power Down Mode
Register
Power On Reset
Cleared to
“
0
”
Initialized based on
the selection in
PSDsoft
Configuration Menu.
Cleared to
“
0
”
Warm Reset
Unchanged
Initialized based on
the selection in
PSDsoft
Configuration Menu.
Cleared to
“
0
”
Power Down Mode
Unchanged
Unchanged
PMMR0, 2
VM Register*
All other registers
Unchanged
By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port C
are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO.
See Waferscale Application Note 54 for more details on JTAG In-System-Programming.
相關(guān)PDF資料
PDF描述
PSD934F2 Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲(chǔ)器系統(tǒng))
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PSD913F2-12B81 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F2-12B81I 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F2-12J 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F2-12JI 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
PSD913F2-12JIT 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:Flash In-System Programmable ISP Peripherals For 8-bit MCUs
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