參數(shù)資料
型號: PSD913F2
英文描述: Configurable Memory System on a Chip for 8-Bit Microcontrollers(用于8位MCU的可配置存儲器系統(tǒng))
中文描述: 在8片位微控制器可配置存儲系統(tǒng)(用于8位微控制器的可配置存儲器系統(tǒng))
文件頁數(shù): 72/94頁
文件大?。?/td> 477K
代理商: PSD913F2
PSD9XX Family
Preliminary Information
68
NOTES:
1.
RD timing has the same timing as DS, LDS, UDS, and PSEN signals.
RD and PSEN have the same timing.
Any input used to select an internal PSD9XX function.
In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
RD timing has the same timing as DS, LDS, and UDS signals.
2.
3.
4.
5.
-90
-15
Turbo
Off
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
t
LVLX
t
AVLX
t
LXAX
t
AVQV
t
SLQV
ALE or AS Pulse Width
20
28
ns
Address Setup Time
(Note 3)
6
10
ns
Address Hold Time
(Note 3)
8
11
ns
Address Valid to Data Valid
(Note 3)
90
150
Add 10
ns
CS Valid to Data Valid
100
150
ns
RD to Data Valid 8-Bit Bus
(Note 5)
32
40
ns
t
RLQV
RD or PSEN to Data Valid 8-Bit Bus,
8-Bit Bus, 8031, 80251
(Note 2)
38
45
ns
t
RHQX
t
RLRH
t
RHQZ
t
EHEL
t
THEH
t
ELTL
RD Data Hold Time
(Note 1)
0
0
ns
RD Pulse Width
(Note 1)
32
38
ns
RD to Data High-Z
(Note 1)
25
30
ns
E Pulse Width
32
38
ns
R/W Setup Time to Enable
10
18
ns
R/W Hold Time After Enable
0
0
ns
t
AVPV
Address Input Valid to Address
Output Delay
(Note 4)
25
32
ns
Read Timing
(5 V ± 10% Versions)
Microcontroller Interface – PSD9XX AC/DC Parameters
(5V ±10% Versions)
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