參數(shù)資料
型號(hào): PSD813F5V-20MT
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝: PLASTIC, QFP-52
文件頁(yè)數(shù): 65/103頁(yè)
文件大小: 1180K
代理商: PSD813F5V-20MT
PSD8XXF2/3/4/5
64/103
Table 33. Status During Power-On Reset, Warm Reset and Power-down Mode
Note: 1. The SR_cod and PeriphMode bits in the VM Register are always cleared to 0 on Power-On Reset or Warm Reset.
Port Configuration
Power-On Reset
Warm Reset
Power-down Mode
MCU I/O
Input mode
Unchanged
PLD Output
Valid after internal PSD
configuration bits are
loaded
Valid
Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out
Tri-stated
Not defined
Data Port
Tri-stated
Peripheral I/O
Tri-stated
Register
Power-On Reset
Warm Reset
Power-down Mode
PMMR0 and PMMR2
Cleared to 0
Unchanged
Macrocells flip-flop status
Cleared to 0 by internal
Power-On Reset
Depends on .re and .pr
equations
Depends on .re and .pr
equations
VM Register1
Initialized, based on the
selection in PSDsoft
Configuration menu
Initialized, based on the
selection in PSDsoft
Configuration menu
Unchanged
All other registers
Cleared to 0
Unchanged
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