參數(shù)資料
型號(hào)： PSD813F5V-20MT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝： PLASTIC, QFP-52
文件頁數(shù)： 13/103頁
文件大?。?/td> 1180K
代理商： PSD813F5V-20MT
17/103
PSD8XXF2/3/4/5
Table 6. I/O Port Latched Address Output Assignments (Note1)
Note: 1. See the section entitled “I/O PORTS”, on page 48, on how to enable the Latched Address Output function.
2. N/A = Not Applicable
Table 7. Register Address Offset
Note: 1. Other registers that are not part of the I/O ports.
MCU
Port A
Port B
Port A (3:0)
Port A (7:4)
Port B (3:0)
Port B (7:4)
8051XA (8-bit)
N/A
Address a7-a4
Address a11-a8
N/A
80C251 (page mode)
N/A
Address a11-a8
Address a15-a12
All other 8-bit multiplexed
Address a3-a0
Address a7-a4
Address a3-a0
Address a7-a4
8-bit non-multiplexed bus
N/A
Address a3-a0
Address a7-a4
Register Name
Port A
Port B
Port C
Port D
Other1
Description
Data In
00
01
10
11
Reads Port pin as input, MCU I/O input mode
Control
02
03
Selects mode between MCU I/O or Address Out
Data Out
04
05
12
13
Stores data for output to Port pins, MCU I/O output
mode
Direction
06
07
14
15
Configures Port pin as input or output
Drive Select
08
09
16
17
Configures Port pins as either CMOS or Open
Drain on some pins, while selecting high slew rate
on other pins.
Input Macrocell
0A
0B
18
Reads Input Macrocells
Enable Out
0C
0D
1A
1B
Reads the status of the output enable to the I/O
Port driver
Output Macrocells
AB
20
READ – reads output of macrocells AB
WRITE – loads macrocell flip-flops
Output Macrocells
BC
21
READ – reads output of macrocells BC
WRITE – loads macrocell flip-flops
Mask Macrocells AB
22
Blocks writing to the Output Macrocells AB
Mask Macrocells BC
23
Blocks writing to the Output Macrocells BC
Primary Flash
Protection
C0
Read only – Primary Flash Sector Protection
Secondary Flash
memory Protection
C2
Read only – PSD8XXFX Security and Secondary
Flash memory Sector Protection
JTAG Enable
C7
Enables JTAG Port
PMMR0
B0
Power Management Register 0
PMMR2
B4
Power Management Register 2
Page
E0
Page Register
VM
E2
Places PSD8XXFX memory areas in Program
and/or Data space on an individual basis.
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