參數(shù)資料
型號(hào)： PSD813F5V-20MT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝： PLASTIC, QFP-52
文件頁數(shù)： 63/103頁
文件大?。?/td> 1180K
代理商： PSD813F5V-20MT
PSD8XXF2/3/4/5
62/103
SRAM Standby Mode (Battery Backup). The
PSD8XXFX supports a battery backup mode in
which the contents of the SRAM are retained in the
event of a power loss. The SRAM has Voltage
Stand-by (VSTBY, PC2) that can be connected to
an external battery. When VCC becomes lower
than VSTBY then the PSD8XXFX automatically
connects to Voltage Stand-by (VSTBY, PC2) as a
power source to the SRAM. The SRAM Standby
Current (ISTBY) is typically 0.5 A. The SRAM data
retention voltage is 2 V minimum. The Battery-on
Indicator (VBATON) can be routed to PC4. This
signal indicates when the VCC has dropped below
VSTBY.
PSD Chip Select Input (CSI, PD2)
PD2 of Port D can be configured in PSDsoft Ex-
press as PSD Chip Select Input (CSI). When Low,
the signal selects and enables the internal Flash
memory, EEPROM, SRAM, and I/O blocks for
READ
or
WRITE
operations
involving
the
PSD8XXFX. A High on PSD Chip Select Input
(CSI, PD2) disables the Flash memory, EEPROM,
and SRAM, and reduces the PSD8XXFX power
consumption. However, the PLD and I/O signals
remain operational when PSD Chip Select Input
(CSI, PD2) is High.
There may be a timing penalty when using PSD
Chip Select Input (CSI, PD2) depending on the
speed grade of the PSD8XXFX that you are using.
See the timing parameter tSLQV in Table 60 or Ta-
Input Clock
The PSD8XXFX provides the option to turn off
CLKIN (PD1) to the PLD to save AC power con-
sumption. CLKIN (PD1) is an input to the PLD
AND Array and the Output Macrocells (OMC).
During Power-down mode, or, if CLKIN (PD1) is
not being used as part of the PLD logic equation,
the clock should be disabled to save AC power.
CLKIN (PD1) is disconnected from the PLD AND
Array or the Macrocells block by setting bits 4 or 5
to a 1 in PMMR0.
Input Control Signals
The PSD8XXFX provides the option to turn off the
input control signals (CNTL0, CNTL1, CNTL2, Ad-
dress Strobe (ALE/AS, PD0) and DBE) to the PLD
to save AC power consumption. These control sig-
nals are inputs to the PLD AND Array. During
Power-down mode, or, if any of them are not being
used as part of the PLD logic equation, these con-
trol signals should be disabled to save AC power.
They are disconnected from the PLD AND Array
by setting bits 2, 3, 4, 5, and 6 to a 1 in PMMR2.
Table 32. APD Counter Operation
APD Enable Bit
ALE PD Polarity
ALE Level
APD Counter
0
X
Not Counting
1
X
Pulsing
Not Counting
1
Counting (Generates PDN after 15 Clocks)
1
0
Counting (Generates PDN after 15 Clocks)
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