參數(shù)資料
型號: PSD813F5V-20MT
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝: PLASTIC, QFP-52
文件頁數(shù): 50/103頁
文件大?。?/td> 1180K
代理商: PSD813F5V-20MT
PSD8XXF2/3/4/5
50/103
Table 19. Port Operating Modes
Note: 1. Can be multiplexed with other I/O functions.
Table 20. Port Operating Mode Settings
Note: 1. N/A = Not Applicable
2. The direction of the Port A,B,C, and D pins are controlled by the Direction Register ORed with the individual output enable product
term (.oe) from the CPLD AND Array.
3. Any of these three methods enables the JTAG pins on Port C.
Port Mode
Port A
Port B
Port C
Port D
MCU I/O
Yes
PLD I/O
McellAB Outputs
McellBC Outputs
Additional Ext. CS Outputs
PLD Inputs
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
Address Out
Yes (A7 – 0)
or (A15 – 8)
No
Address In
Yes
Data Port
Yes (D7 – 0)
No
Peripheral I/O
Yes
No
JTAG ISP
No
Yes1
No
Mode
Defined in
PSDabel
Defined in
PSD8XXFX
Configuration
Control
Register
Setting
Direction
Register
Setting
VM
Register
Setting
JTAG Enable
MCU I/O
Declare pins only
N/A1
0
1 = output,
0 = input
(Note 2)
N/A
PLD I/O
Logic equations
N/A
(Note 2)
N/A
Data Port (Port A)
N/A
Specify bus type
N/A
Address Out
(Port A,B)
Declare pins only
N/A
1
1 (Note 2)
N/A
Address In
(Port A,B,C,D)
Logic for equation
Input Macrocells
N/A
Peripheral I/O
(Port A)
Logic equations
(PSEL0 & 1)
N/A
PIO bit = 1
N/A
JTAG ISP (Note 3)
JTAGSEL
JTAG
Configuration
N/A
JTAG_Enable
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