參數(shù)資料
型號： PSD813F5V-20MT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
封裝： PLASTIC, QFP-52
文件頁數(shù)： 62/103頁
文件大?。?/td> 1180K
代理商： PSD813F5V-20MT
61/103
PSD8XXF2/3/4/5
PLD Power Management
The power and speed of the PLDs are controlled
by the Turbo bit (bit 3) in PMMR0. By setting the
bit to 1, the Turbo mode is off and the PLDs con-
sume the specified stand-by current when the in-
puts are not switching for an extended time of
70ns. The propagation delay time is increased by
10ns after the Turbo bit is set to 1 (turned off) when
the inputs change at a composite frequency of less
than 15 MHz. When the Turbo bit is reset to 0
(turned on), the PLDs run at full power and speed.
The Turbo bit affects the PLD’s DC power, AC
power, and propagation delay.
Blocking MCU control signals with the bits of
PMMR2 can further reduce PLD AC power con-
sumption.
Table 30. Power Management Mode Registers PMMR0 (Note 1)
Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers.
Table 31. Power Management Mode Registers PMMR2 (Note 1)
Note: 1. The bits of this register are cleared to zero following Power-up. Subsequent Reset (RESET) pulses do not clear the registers.
Bit 0
X
0
Not used, and should be set to zero.
Bit 1
APD Enable
0 = off Automatic Power-down (APD) is disabled.
1 = on Automatic Power-down (APD) is enabled.
Bit 2
X
0
Not used, and should be set to zero.
Bit 3
PLD Turbo
0 = on PLD Turbo mode is on
1 = off PLD Turbo mode is off, saving power.
Bit 4
PLD Array clk
0 = on
CLKIN (PD1) input to the PLD AND Array is connected. Every change of CLKIN
(PD1) Powers-up the PLD when Turbo bit is 0.
1 = off CLKIN (PD1) input to PLD AND Array is disconnected, saving power.
Bit 5
PLD MCell clk
0 = on CLKIN (PD1) input to the PLD macrocells is connected.
1 = off CLKIN (PD1) input to PLD macrocells is disconnected, saving power.
Bit 6
X
0
Not used, and should be set to zero.
Bit 7
X
0
Not used, and should be set to zero.
Bit 0
X
0
Not used, and should be set to zero.
Bit 1
X
0
Not used, and should be set to zero.
Bit 2
PLD Array
CNTL0
0 = on Cntl0 input to the PLD AND Array is connected.
1 = off Cntl0 input to PLD AND Array is disconnected, saving power.
Bit 3
PLD Array
CNTL1
0 = on Cntl1 input to the PLD AND Array is connected.
1 = off Cntl1 input to PLD AND Array is disconnected, saving power.
Bit 4
PLD Array
CNTL2
0 = on Cntl2 input to the PLD AND Array is connected.
1 = off Cntl2 input to PLD AND Array is disconnected, saving power.
Bit 5
PLD Array
ALE
0 = on ALE input to the PLD AND Array is connected.
1 = off ALE input to PLD AND Array is disconnected, saving power.
Bit 6
PLD Array
DBE
0 = on DBE input to the PLD AND Array is connected.
1 = off DBE input to PLD AND Array is disconnected, saving power.
Bit 7
X
0
Not used, and should be set to zero.
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