參數(shù)資料
型號: PSD813F2-15JT
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
封裝: PLASTIC, LCC-52
文件頁數(shù): 97/103頁
文件大?。?/td> 1180K
代理商: PSD813F2-15JT
93/103
PSD8XXF2/3/4/5
Figure 46. Reset (RESET) Timing
Table 64. Reset (RESET) Timing (5V devices)
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Table 65. Reset (RESET) Timing (3V devices)
Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles.
2. Warm reset aborts Flash memory Program or Erase cycles, and puts the device in READ Mode.
Table 66. VSTBYON Timing (5V devices)
Note: 1. VSTBYON timing is measured at VCC ramp rate of 2 ms.
Table 67. VSTBYON Timing (3V devices)
Note: 1. VSTBYON timing is measured at VCC ramp rate of 2 ms.
Symbol
Parameter
Conditions
Min
Max
Unit
tNLNH
RESET Active Low Time 1
150
ns
tNLNH–PO
Power On Reset Active Low Time
1
ms
tNLNH–A
Warm Reset (on the PSD834Fx) 2
25
s
tOPR
RESET High to Operational Device
120
ns
Symbol
Parameter
Conditions
Min
Max
Unit
tNLNH
RESET Active Low Time 1
300
ns
tNLNH–PO
Power On Reset Active Low Time
1
ms
tNLNH–A
Warm Reset (on the PSD834Fx) 2
25
s
tOPR
RESET High to Operational Device
300
ns
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tBVBH
VSTBY Detection to VSTBYON Output High
(Note 1)
20
s
tBXBL
VSTBY Off Detection to VSTBYON Output
Low
(Note 1)
20
s
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tBVBH
VSTBY Detection to VSTBYON Output High
(Note 1)
20
s
tBXBL
VSTBY Off Detection to VSTBYON Output
Low
(Note 1)
20
s
tNLNH-PO
tOPR
AI02866b
RESET
tNLNH
tNLNH-A
tOPR
VCC
V
CC(min)
Power-On Reset
Warm Reset
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