參數(shù)資料
型號： PSD813F2-15JT
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 24/103頁
文件大小： 1180K
代理商： PSD813F2-15JT
27/103
PSD8XXF2/3/4/5
Memory Select Configuration for MCUs with
Separate Program and Data Spaces. The 8031
and compatible family of MCUs, which includes
the 80C51, 80C151, 80C251, and 80C51XA, have
separate address spaces for Program memory
(selected using Program Select Enable (PSEN,
CNTL2)) and Data memory (selected using Read
Strobe (RD, CNTL1)). Any of the memories within
the PSD8XXFX can reside in either space or both
spaces. This is controlled through manipulation of
the VM register that resides in the CSIOP space.
The VM register is set using PSDsoft Express to
have an initial value. It can subsequently be
changed by the MCU so that memory mapping
can be changed on-the-fly.
For example, you may wish to have SRAM and pri-
mary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the primary and
secondary Flash memories. This is easily done
with the VM register by using PSDsoft Express
Configuration to configure it for Boot-up and hav-
ing the MCU change it when desired. Table 12 de-
scribes the VM Register.
Table 12. VM Register
Configuration Modes for MCUs with Separate
Program and Data Spaces. Separate
Space
Modes. Program space is separated from Data
space. For example, Program Select Enable
(PSEN, CNTL2) is used to access the program
code from the primary Flash memory, while Read
Strobe (RD, CNTL1) is used to access data from
the secondary Flash memory, SRAM and I/O Port
blocks. This configuration requires the VM register
to be set to 0Ch (see Figure 8).
Figure 8. 8031 Memory Modules – Separate Space
Bit 7
PIO_EN
Bit 6
Bit 5
Bit 4
Primary
FL_Data
Bit 3
Secondary
EE_Data
Bit 2
Primary
FL_Code
Bit 1
Secondary
EE_Code
Bit 0
SRAM_Code
0 = disable
PIO mode
not used
0 = RD
can’t
access
Flash
memory
0 = RD can’t
access Secondary
Flash memory
0 = PSEN
can’t
access
Flash
memory
0 = PSEN can’t
access Secondary
Flash memory
0 = PSEN
can’t
access
SRAM
1= enable
PIO mode
not used
1 = RD
access
Flash
memory
1 = RD access
Secondary Flash
memory
1 = PSEN
access
Flash
memory
1 = PSEN access
Secondary Flash
memory
1 = PSEN
access
SRAM
Primary
Flash
Memory
DPLD
Secondary
Flash
Memory
SRAM
RS0
CSBOOT0-3
FS0-FS7
CS
OE
RD
PSEN
OE
AI02869C
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