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參數(shù)資料
| 型號(hào)： | PSD813F2-15JT |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁(yè)數(shù)： | 96/103頁(yè) |
| 文件大?。?/td> | 1180K |
| 代理商： | PSD813F2-15JT |
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PSD8XXF2/3/4/5
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Figure 45. Peripheral I/O WRITE Timing
Table 62. Port A Peripheral Data Mode WRITE Timing (5V devices)
Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
Table 63. Port A Peripheral Data Mode WRITE Timing (3V devices)
Note: 1. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode).
2. WR has the same timing as the E, LDS, UDS, WRL, and WRH signals.
3. Any input used to select Port A Data Peripheral mode.
4. Data is already stable on Port A.
5. Data stable on ADIO pins to data on Port A.
Symbol
Parameter
Conditions
-70
-90
-15
Unit
Min
Max
Min
Max
Min
Max
tWLQV–PA
WR to Data Propagation Delay
(Note 2)
25
35
40
ns
tDVQV–PA
Data to Port A Data Propagation Delay
(Note 5)
22
30
38
ns
tWHQZ–PA
WR Invalid to Port A Tri-state
(Note 2)
20
25
33
ns
Symbol
Parameter
Conditions
-12
-15
-20
Unit
Min
Max
Min
Max
Min
Max
tWLQV–PA
WR to Data Propagation Delay
(Note 2)
42
45
55
ns
tDVQV–PA
Data to Port A Data Propagation Delay
(Note 5)
38
40
45
ns
tWHQZ–PA
WR Invalid to Port A Tri-state
(Note 2)
33
35
ns
tDVQV (PA)
tWLQV
(PA)
tWHQZ (PA)
ADDRESS
DATA OUT
A / D BUS
WR
PORT A
DATA OUT
ALE /AS
AI02898
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