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參數(shù)資料
| 型號(hào)： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 99/162頁(yè) |
| 文件大?。?/td> | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
102
PM2329 ClassiPI Network Classification Processor Datasheet
Result Available
This bit is set when there is at least one result in the Result FIFO. When the PM2329 is operating in
multi-channel mode, this bit when set indicates that at least one of the Result FIFOs have results
available. The Channel Result Available bit in the Channel Status Registers can be used to determine
channel(s) for which the Result(s) are available.
This bit is cleared when all the individual Channel Result Available bits are clear.
OC Sequence Terminated
This bit is set when the packet processing on the current packet is complete. This bit is cleared when this
register is read. This also causes the OC Sequence Interrupt, if enabled, to be deasserted.
Status Valid
This bit is set to indicate the status registers has at least one status bit set. This bit is cleared when all
other status bits in this register are clear.
4.2.2.12 Operation Control Register (OPCR; 8248h)
Access Mode: Read/Write, Global
Notes:
a. This bit is set to
‘
1
’
when the reset signal RESET* is asserted, it is reset to
‘
0
’
eight SCLK cycles after reset signal is deasserted.
This register controls the operation modes of the PM2329. This register should be written by the processor
when it detects the PM2329 is idle (STSR[4]= 1) and prior to supplying the packet data to the device and it
should not be updated by the processor until after the EOP for the packet has been transferred to the device.
The bits in this register are as follows:
Soft Reset
Writing a 1 to this bit causes the chip to perform a soft reset internally. On reading the register, the bit
indicates 1 if a soft reset or hard reset is in progress. The bit automatically resets to 0 eight SCLK cycles
when the internal reset operation is done. Soft reset forces all the registers to their Reset state and the
Packet Buffer and Result FIFOs are cleared. Soft reset does not affect strap option pins, they are
sampled on hard reset only.
Bit
Range
63
62
61:4
Size
1
1
58
Name
Value after
Reset
See Note (a)
See Note (a)
000 0000 0000
0000h
1
1
1
0
Soft Reset
Hard Reset Status (RO)
(Reserved)
3
2
1
0
1
1
1
1
Enable Multi-Channel Mode
Enable PI Field
Enable OCC Field
Direction Specifier
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