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參數(shù)資料
| 型號： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 110/162頁 |
| 文件大?。?/td> | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
113
PM2329 ClassiPI Network Classification Processor Datasheet
4.2.2.17 Alternate OCC Register (AOCC; 8270h)
Access Mode: Read/Write, Global
Writes to this register are recognized by the device only if the current OC execution has reached halt state-
-either a break or a wait condition--as a result of one of the following two control settings:
1.
OC Trace Enable is set (Trace On), or
2.
OC Trace Enable is reset and OC Sequence Mode is set (Processor controlled sequencing On).
When a break condition (end of OC execution) occurs, the processor can either Terminate Sequence or
Continue Sequence. When a wait condition (end of OC sequence) occurs, the processor can either
Terminate Sequence or Start New Sequence.
The processor writes to the AOCC register to issue Terminate Sequence, Continue Sequence or Start New
Sequence commands in the following manner.
1.
To issue a Terminate Sequence command that terminates the current packet processing, the processor
writes an EPP (End of Packet Processing) word (0000 XXXX XXXX XXXXh) to this register.
2.
To issue a Continue Sequence command that continues the execution of remaining OCs in the sequence,
the processor can write any non-EPP word to this register.
3.
To issue a Start New Sequence command that starts executing a new OCC sequence on the current
packet, the processor can write a new OCC word to this register. The format of this register is identical
to the OCC Register format described earlier.
Note: To issue the Continue Sequence or Start New Sequence commands, the processor writes a non-EPP
word to the AOCC. This word is interpreted as
“
Continue Sequence
”
if a break condition has occurred
(that is, the OC just executed is not the the last OC of the programmed sequence). It is interpreted as
“
Start
New Sequence
”
if a wait condition has occurred (that is, the OC just executed is the last OC of the
programmed sequence).
In the automated OC sequencing operations (Trace OC Enable is reset and OC Sequence Mode bit is reset),
this register is ignored.
Bit
Range
63:0
Size
64
Name
Value after Reset
0000 0000 0000 0000h
OC Conductor
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