- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370008 > PM2329 Telecommunication IC PDF資料下載
參數(shù)資料
| 型號(hào)： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 59/162頁(yè) |
| 文件大小： | 1581K |
| 代理商： | PM2329 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)當(dāng)前第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
62
PM2329 ClassiPI Network Classification Processor Datasheet
The multi-channel operation of the PM2329 is enabled by setting a bit in the Operation Control Register to
enable the multi-channel mode. Note that packet data transfer when multi-channel mode is enabled must
be done using processor cycles. Packet Source (DMA) transfers are not supported in this case.
In the multi-channel mode, the 8 KB input buffer is organized as 32 segments of 256 bytes each. Packet
Input Buffer Registers for each segment are provided so that the external processor(s) may write to any
segment (based on the context that is writing the packet). Similarly, the 128 entry results FIFO gets
organized into 32 segments of 4 entries each. The combination of the input buffer and the associated results
segment defines a channel. These channels are numbered 0 through 31. Consequently, 32 simultaneous
channels can co-exist and be used by 32 independent tasks/contexts. The registers used to load the packet,
retrieve results, and check the packet processing status are organized in a per-channel fashion into channel-
oriented register groups. This allows multiple contexts on the external processor to access their channel
registers simply by using the appropriate base address for that channel group.
The PM2329 processes the packets in the order in which packet transfers complete. Results from packet
processing are then sent to the appropriate segment in the Results FIFO. The results for a channel are made
available through an OC Results FIFO Read Port for each channel.
The SCHNUM[4:0] and SCHSTB pins on the PM2329 provide the required support to accomplish a
hardware-based handshake between the PM2329 and the processor. For processors equipped to handle
such handshake signals, this interface awakens a context whenever its packet processing results are ready.
If the processor does not implement this interface, a Channel Status Register can be read by any context to
determine the status of the Packet Input Buffers and result FIFOs for that channel.
Concatenation of segments is supported to allow any channel to transfer a packet larger than 256 bytes or
to accumulate more than 4 results. This is accomplished using the Channel Assignment Register. This
allows any number of adjacent channels to be concatenated to work as a single larger channel. When 4
channels are concatenated, for example, the Packet Input Buffer will appear to be 1 KB in length and the
OC Results will appear to be a 16 deep FIFO.
3.1.4 Channel Input, Output and Status Mechanism
Each channel (0 through 31) has its pre-assigned packet input buffer available for loading after reset and
after the previously loaded packet has been processed. Since the write ports associated with the packet
input buffers share the processor bus, only one of them can be written to at a time; however, they can be
loaded in an interleaved fashion. Once a packet has been loaded by a context, the context must wait until
the processing for this packet is complete as indicated by OC Sequence Terminated bit, before loading the
next packet for its assigned channel.
The diagram below shows the operation of status bits used for Packet input and Result output.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PM239P | Analog Comparator |
| PM30RHC060 | TRANSISTOR | IGBT POWER MODULE | 3-PH BRIDGE | 600V V(BR)CES | 30A I(C) |
| PM3321-QC | DATA CROSS CONNECT|LDCC|84PIN|PLASTIC |
| PM355AJ | Voltage-Feedback Operational Amplifier |
| PM355AZ | Voltage-Feedback Operational Amplifier |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PM233-155.52M | 制造商:CONNOR-WINFIELD 制造商全稱:Connor-Winfield Corporation 功能描述:5.0x7.0mm Surface Mount LVPECL Clock Oscillator Series |
| PM2379-001 | 制造商:Delphi Corporation 功能描述:TAPE MARK WHT |
| PM238 | 制造商:PURDY 制造商全稱:PURDY 功能描述:AC Fans and Blowers |
| PM238-115-1751BT-4 | 制造商:INTERFAN 功能描述:Fan, AC, 115V, 172x150x51mm, Obround, 238CFM, 3100RPM, 55dBA, Terminal Block |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。