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參數(shù)資料
| 型號： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 116/162頁 |
| 文件大?。?/td> | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
119
PM2329 ClassiPI Network Classification Processor Datasheet
If the OC Sequence Halted bit is 1 and this bit is 1, the PM2329 has reached a wait condition for the
corresponding channel--it has completed execution of the previous OC and this just completed OC was
the last OC in the specified sequence.
Channel Packet Buffer Available
This bit is set to indicate that the corresponding Packet Buffer is empty. A Packet Buffer is empty as
soon as the OC processing for that channel is complete. Depending on the single- vs. multi-channel
mode setting, the behavior of the PBA bit is different as explained below.
In single-channel mode, the PBA bit is set as long as a 256 byte block is available in the Packet Buffer.
This bit is cleared when the first packet data word is written to the last available 256 byte block in the
Packet Buffer.
In multi-channel mode, the PBA bit is set as long as the 256 byte block corresponding to this channel is
available. This bit is cleared when the first packet data word is written to the 256 byte block in the
Packet Buffer. In multi channel mode with concatenation enabled, this bit (for the lowest numbered
channel in the concatenated chain, all other concatenated channels in this chain are not used) behaves
the same as the multi channel mode except the block size now refers to (N x 256) bytes where N is the
number of channels concatenated together.
Channel Result Available
This bit is set whenever one or more results are available in the corresponding Results FIFO. This bit is
cleared when all of the results are read out by the processor.
Channel OC Sequence Terminated
This bit is set whenever the packet processing is completed and all the results have been transferred into
the Results FIFO corresponding to that channel. This bit is cleared when the Channel Status Register is
read by the processor or the EOP for the corresponding channel is detected.
The STSR contains summary status of all CSRs. Note that the OC Sequence Terminated bit in the STSR is
set when any of the Channel OC Sequence Terminated bit are set. Each OC Sequence Terminated bit is
cleared when the corresponding register is read. If in response to an interrupt generated due to the OC
Sequence Terminated condition, the processor reads the STSR (thereby clearing the OC Sequence
Terminated bit in the STSR) without reading the CSRs (thus leaving the OC Sequence Terminated bit set in
the CSRs) and another OC sequence is terminated, the PM2329 will set the OC Sequence Terminated bit in
the STSR.
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