
PI7C9X20505GP
5Port-5Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 9 of 81
June 2009 – Revision 1.5
Pericom Semiconductor
TABLE OF FIGURES
FIGURE 6-1 SMBUS ARCHITECTURE IMPLEMENTATION ON PI7C9X20505GP............................................................32
FIGURE 13-1 BOTTOM VIEW DRAWING ........................................................................................................................79
FIGURE 13-2 PACKAGE OUTLINE DRAWING .................................................................................................................80
LIST OF TABLES
TABLE 5-1 NOMINAL DRIVER CURRENT VALUES (INOM)............................................................................................18
TABLE 5-2 RATIO OF ACTUAL CURRENT AND NOMINAL CURRENT.............................................................................18
TABLE 5-3 DE-EMPHASIS LEVEL VERSUS DEQ [3:0]...................................................................................................19
TABLE 5-4 SUMMARY OF PCI EXPRESS ORDERING RULES..........................................................................................22
TABLE 6-1 SMBUS ADDRESS PIN CONFIGURATION ....................................................................................................32
TABLE 7-1 REGISTER ARRAY LAYOUT FOR VC ARBITRATION....................................................................................67
TABLE 7-2 TABLE ENTRY SIZE IN 4 BITS.....................................................................................................................68
TABLE 8-1 INPUT CLOCK REQUIREMENTS ...................................................................................................................70
TABLE 10-1 INSTRUCTION REGISTER CODES................................................................................................................72
TABLE 10-2 JTAG DEVICE ID REGISTER .....................................................................................................................72
TABLE 10-3 JTAG BOUNDARY SCAR REGISTER DEFINITION ........................................................................................73
TABLE 12-1 ABSOLUTE MAXIMUM RATINGS................................................................................................................76
TABLE 12-2 DC ELECTRICAL CHARACTERISTICS .........................................................................................................76
TABLE 12-3 TRANSMITTER CHARACTERISTICS............................................................................................................77
TABLE 12-4 RECEIVER CHARACTERISTICS ..................................................................................................................78