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參數(shù)資料
| 型號(hào)： | PI7C9X20505GPBNDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 4/81頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 256BGA |
| 產(chǎn)品變化通告： | Copper Wire Change 26/Sept/2011 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 系列： | GreenPacket™ |
| 應(yīng)用： | 封裝開關(guān)，5 端口/5 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 256-BGA |
| 供應(yīng)商設(shè)備封裝： | 256-PBGA（17x17） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20505GP
5Port-5Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 12 of 81
June 2009 – Revision 1.5
Pericom Semiconductor
3 PIN DESCRIPTION
3.1
PCI EXPRESS INTERFACE SIGNALS
NAME
PIN
TYPE
DESCRIPTION
REFCLKP
REFCLKN
A16
A15
I
Reference Clock Input Pairs: Connects to external 100MHz
differential clock.
The input clock signals must be delivered to the clock buffer cell
through an AC-coupled interface so that only the AC information of
the clock is received, converted, and buffered. It is recommended that a
0.1uF be used in the AC-coupling.
PERP [4:0]
D16, K16,
M15, T13,
A13
I
PERN [4:0]
D15, K15,
M16, T12,
B13
I
PCI Express Data Serial Input Pairs: Differential data receive
signals in five ports.
Port 0 (Upstream Port) is PERP[0] and PERN[0]
Port 1 (Downstream Port) is PERP[1] and PERN[1]
Port 2 (Downstream Port) is PERP[2] and PERN[2]
Port 3 (Downstream Port) is PERP[3] and PERN[3]
Port 4 (Downstream Port) is PERP[4] and PERN[4]
PETP [4:0]
F15, H15,
P16, T15,
A11
O
PETN [4:0]
F16, H16,
P15, T16,
B11
O
PCI Express Data Serial Output Pairs: Differential data transmit
signals in five ports.
Port 0 (Upstream Port) is PETP[0] and PETN[0]
Port 1 (Downstream Port) is PETP[1] and PETN[1]
Port 2 (Downstream Port) is PETP[2] and PETN[2]
Port 3 (Downstream Port) is PETP[3] and PETN[3]
Port 4 (Downstream Port) is PETP[4] and PETN[4]
WAKEUP_L
F2
I
Wakeup Signal (Active LOW): When WAKEUP_L is asserted, the
upstream port has to generate a Beacon that is propagated to the Root
Complex/Power Management Controller. Pin has an internal pull-up.
RESET_L
E4
I
System Reset (Active LOW): When RESET_L is asserted, the
internal states of whole chip except sticky logics are initialized.
DWNRST_L [4:1]
E5, D5, E6,
D6
O
Downstream Device Reset (Active LOW): It provides a reset signal
to the devices connected to the downstream ports of Switch. The signal
is active when either RESET_L is asserted or the device is just plugged
into the Switch. DWNRST_L [x] corresponds to Portx, where x=
1,2,3,4.
3.2
PORT CONFIGURATION SIGNALS
NAME
PIN
TYPE
DESCRIPTION
VC1_EN
F4
I
Virtual Channel 1 Enable: The chip provides the capability to
support virtual channel 1 (VC1), in addition to the standard virtual
channel 0. When this pin is asserted high, Virtual Channel 1 is enabled,
and virtual channel resource sharing is not available. When it is
asserted low, the chip would allocate the additional VC1 resource to
VC0, and VC1 capability is disabled. The pin has internal pull-down.
SLOT_IMP [4:1]
*T6, G4, G2,
G1
I
Slot Implemented: It decides if the downstream port is connected to
slot. SLOT_IMP [x] is correspondent to Portx, where x= 1,2,3,4. When
SLOT_IMP [x] is high, the Portx is connected to slot. The strapping
pin SLOT_IMP[4] is shared with PWR_IND[1]. By default,
downstream Port1, Port2, Port3, and Port4 are implemented with slots.
SLOT_IMP[4] has internal pull-down, and SLOT_IMP[3:1] have
internal pull-up.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C9X20508GPANDE | 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Rail/Tube |
| PI7C9X20508GPBEVB | 制造商:Pericom Semiconductor Corporation 功能描述:EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20508GPBNDE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 5port 8lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20508GPNDE | 制造商:Pericom Semiconductor Corporation 功能描述:5-PORT, 8-LANE, GREENPACKET- PCIE PACKET SWITCH - Trays |
| PI7C9X2G303ELAEVB | 制造商:Pericom Semiconductor Corporation 功能描述:Switch IC Development Tools Eval Kit for PI7C9X2G303ELA |
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