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參數(shù)資料
| 型號： | PI7C9X20505GPBNDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 36/81頁 |
| 文件大小： | 0K |
| 描述： | IC PCIE PACKET SWITCH 256BGA |
| 產(chǎn)品變化通告： | Copper Wire Change 26/Sept/2011 |
| 標準包裝： | 90 |
| 系列： | GreenPacket™ |
| 應用： | 封裝開關，5 端口/5 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 256-BGA |
| 供應商設備封裝： | 256-PBGA（17x17） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20505GP
5Port-5Lane PCI Express Switch
GreenPacket
TM Family
Datasheet
Page 41 of 81
June 2009 – Revision 1.5
Pericom Semiconductor
7.2.27
INTERRUPT PIN REGISTER – OFFSET 3Ch
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Interrupt Pin
RO
The Switch implements INTA virtual wire interrupt signals to represent
hot-plug events at downstream ports. The default value on the downstream
ports may be changed by SMBus or auto-loading from EEPROM.
Reset to 00h.
7.2.28
BRIDGE CONTROL REGISTER – OFFSET 3Ch
BIT
FUNCTION
TYPE
DESCRIPTION
16
Parity Error
Response
RW
0b: Ignore Poisoned TLPs on the secondary interface
1b: Enable the Poisoned TLPs reporting and detection on the secondary
interface
Reset to 0b.
17
S_SERR# enable
RW
0b: Disables the forwarding of EER_COR, ERR_NONFATAL and
ERR_FATAL from secondary to primary interface
1b: Enables the forwarding of EER_COR, ERR_NONFATAL and
ERR_FATAL from secondary to primary interface
Reset to 0b.
18
ISA Enable
RW
0b: Forwards downstream all I/O addresses in the address range defined by
the I/O Base, I/O Base, and Limit registers
1b: Forwards upstream all I/O addresses in the address range defined by the
I/O Base and Limit registers that are in the first 64KB of PCI I/O address
space (top 768 bytes of each 1KB block)
Reset to 0b.
19
VGA Enable
RW
0: Ignores access to the VGA memory or IO address range
1: Forwards transactions targeted at the VGA memory or IO address range
VGA memory range starts from 000A 0000h to 000B FFFFh
VGA IO addresses are in the first 64KB of IO address space.
AD [9:0] is in the ranges 3B0 to 3BBh and 3C0h to 3DFh.
Reset to 0b. Please note that this bit is reserved in Port 2, Port 3 and Port 4.
20
VGA 16-bit decode
RW
0b: Executes 10-bit address decoding on VGA I/O accesses
1b: Executes 16-bit address decoding on VGA I/O accesses
Reset to 0b. Please note that this bit is reserved in Port 2, Port 3 and Port 4.
21
Master Abort Mode
RO
Does not apply to PCI Express. Must be hardwired to 0b.
22
Secondary Bus Reset
RW
0b: Does not trigger a hot reset on the corresponding PCI Express Port
1b: Triggers a hot reset on the corresponding PCI Express Port
At the downstream port, it asserts PORT_RST# to the attached downstream
device.
At the upstream port, it asserts the PORT_RST# at all the downstream
ports.
Reset to 0b.
23
Fast Back-to-Back
Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
24
Primary Master
Timeout
RO
Does not apply to PCI Express. Must be hardwired to 0b.
25
Secondary Master
Timeout
RO
Does not apply to PCI Express. Must be hardwired to 0b.
26
Master Timeout
Status
RO
Does not apply to PCI Express. Must be hardwired to 0b.
27
Discard Timer
SERR# enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
31:28
Reserved
RO
Reset to 0h.
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相關代理商/技術參數(shù) |
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