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參數(shù)資料
| 型號(hào)： | PI7C9X20303ULAZPE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 52/77頁 |
| 文件大小： | 0K |
| 描述： | IC PCIE PACKET SWITCH 132TQFN |
| 標(biāo)準(zhǔn)包裝： | 168 |
| 系列： | UltraLo™ |
| 應(yīng)用： | 封裝開關(guān)，3 端口/3 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 132-VFQFN 雙排裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 132-TQFN-EP（10x10） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 56 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
9:8
Power Indicator
Control
RW
Controls the display of Power Indicator.
00b: Reserved
01b: On
10b: Blink
11b: Off
Writes to this register also cause the Port to send the
POWER_INDICATOR_* Messages.
Reset to 11b.
10
Power Controller
Control
RW
0b: reset the power state of the slot (Power On)
1b: set the power state of the slot (Power Off)
Reset to 0b.
11
Reserved
RO
Reset to 0b.
12
Data Link Layer
State Changed
Enable
RW
If the Data Link Layer Link Active capability is implemented, when set to 1b,
this field enables software notification when Data Link Layer Link Active
field is changed.
Reset to 0b.
15:13
Reserved
RO
Reset to 000b
7.2.75
SLOT STATUS REGISTER (Downstream Port Only) – OFFSET F8h
BIT
FUNCTION
TYPE
DESCRIPTION
16
Attention Button
Pressed
RW1C
When set, it indicates the Attention Button is pressed.
Reset to 0b.
17
Power Fault Detected
RW1C
When set, it indicates a Power Fault is detected.
Reset to 0b.
18
MRL Sensor
Changed
RO
When set, it indicates a MRL Sensor Changed is detected.
Reset to 0b.
19
Presence Detect
Changed
RW1C
When set, it indicates a Presence Detect Changed is detected.
Reset to 0b.
20
Command
Completed
RW1C
When set, it indicates the Hot-Plug Controller completes an issued command.
Reset to 0b.
21
MRL Sensor State
RO
Reflects the status of MRL Sensor.
0b: MRL Closed
1b: MRL Opened
Reset to 0b.
22
Presence Detect State
RO
Indicates the presence of a card in the slot.
0b: Slot Empty
1b: Card Present in slot
This register is implemented on all Downstream Ports that implement slots.
For Downstream Ports not connected to slots (where the Slot Implemented bit
of the PCI Express Capabilities register is 0b), this bit returns 1b.
Reset to 1b.
23
Reserved
RO
Reset to 0.
24
Data Link Layer
State Changed
RW1C
This bit is set when the value reported in the Data Link Layer Link Active
field of the Link Status register is changed.
31:25
Reserved
RO
Reset to 0
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