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參數(shù)資料
| 型號(hào)： | PI7C9X20303ULAZPE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 4/77頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE PACKET SWITCH 132TQFN |
| 標(biāo)準(zhǔn)包裝： | 168 |
| 系列： | UltraLo™ |
| 應(yīng)用： | 封裝開(kāi)關(guān)，3 端口/3 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 132-VFQFN 雙排裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 132-TQFN-EP（10x10） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 12 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
3 PIN DESCRIPTION
3.1
PCI EXPRESS INTERFACE SIGNALS
NAME
PIN
TYPE
DESCRIPTION
REFCLKP
REFCLKN
B42,
B43
I
Reference Clock Input Pairs: Connect to external 100MHz
differential clock.
The input clock signals must be delivered to the clock buffer cell
through an AC-coupled interface so that only the AC information of
the clock is received, converted, and buffered. It is recommended that a
0.1uF be used in the AC-coupling.
PERP [2:0]
A68, B53,
A58
I
PERN [2:0]
B57, A64,
B48
I
PCI Express Data Serial Input Pairs: Differential data receive
signals in three ports.
Port 0 (Upstream Port) is PERP[0] and PERN[0]
Port 1 (Downstream Port) is PERP[1] and PERN[1]
Port 2 (Downstream Port) is PERP[2] and PERN[2]
PETP [2:0]
B56, B52,
A60
O
PETN [2:0]
A66, A62,
A61
O
PCI Express Data Serial Output Pairs: Differential data transmit
signals in three ports.
Port 0 (Upstream Port) is PETP[0] and PETN[0]
Port 1 (Downstream Port) is PETP[1] and PETN[1]
Port 2 (Downstream Port) is PETP[2] and PETN[2]
PERST_L
A25
I
System Reset (Active LOW): When PERST_L is asserted, the
internal states of whole chip except sticky logics are initialized.
DWNRST_L [2:1]
B44, A52
O
Downstream Device Reset (Active LOW): It provides a reset signal
to the devices connected to the downstream ports of Switch. The signal
is active when either PERST_L is asserted or the device is just plugged
into the Switch. DWNRST_L [x] corresponds to Portx, where x= 1,2.
3.2
PORT CONFIGURATION SIGNALS
NAME
PIN
TYPE
DESCRIPTION
SLOTCLK
B59
I
Slot Clock Configuration: It determines if the downstream component
uses the same physical reference clock that the platform provides on
the connector. When SLOTCLK is high, the platform reference clock is
employed. By default, all downstream ports use the same physical
reference clock provided by platform. The pin has internal pull-down.
3.3
MISCELLANEOUS SIGNALS
NAME
PIN
TYPE
DESCRIPTION
EECLK
A23
O
EEPROM Clock: Clock signal to the EEPROM interface.
EEPD
B19
I/O
EEPROM Data: Bi-directional serial data interface to and from the
EEPROM. The pin is set to 1 by default. The pin has internal pull-up.
SMBCLK
B7
I
SMBus Clock: System management Bus Clock. The pin has internal
pull-up.
SMBDATA
B8
I/O
SMBus Data: Bi-directional System Management Bus Data. The pin
has internal pull-up.
SCAN_EN
A31
I/O
Full-Scan Enable Control: For normal operation, SCAN_EN is an
output with a value of “0”. SCAN_EN becomes an input during
manufacturing testing.
PORTERR [2:0]
B24, A27,
A26
O
Port PHY Error Status: These pins are used to display the PHY Error
status of the ports. When PORTERR is flashing (alternating high and
low signals), it indicates that a PHY error is detected. When it is low,
no PHY error is detected. PORTERR [x] is correspondent to Port x,
where x=0,1,2.
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| PI7C9X20303ULAZPEX | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 3port 3lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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| PI7C9X20404GPBNBE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20404SLCEVB | 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20404SLCFDE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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