TM Family Datasheet Page 31 of 77 August 2009 – Re" />
參數(shù)資料
型號(hào): PI7C9X20303ULAZPE
廠商: Pericom
文件頁數(shù): 25/77頁
文件大小: 0K
描述: IC PCIE PACKET SWITCH 132TQFN
標(biāo)準(zhǔn)包裝: 168
系列: UltraLo™
應(yīng)用: 封裝開關(guān),3 端口/3 線道
接口: PCI Express
封裝/外殼: 132-VFQFN 雙排裸露焊盤
供應(yīng)商設(shè)備封裝: 132-TQFN-EP(10x10)
包裝: 托盤
安裝類型: 表面貼裝
PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 31 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
31 –24
23 – 16
15 - 8
7 –0
BYTE OFFSET
Reserved
C8h – D7h
GPIO Data and Control
D8h
EEPROM Data
EEPROM Address
EEPROM Control
DCh
PCI Express Capabilities Register
Next Item Pointer=00
Capability ID=10
E0h
Device Capabilities
E4h
Device Status
Device Control
E8h
Link Capabilities
ECh
Link Status
Link Control
F0h
Slot Capabilities
F4h
Slot Status
Slot Control
F8h
Reserved
FCh
Other than the PCI 2.3 compatible configuration space header, the Switch also implements PCI
express extended configuration space header, which includes advanced error reporting, virtual channel,
and power budgeting capability registers. The following table details the allocation of the register
fields of PCI express extended capability space header. The first extended capability always begins at
offset 100h with a PCI Express Enhanced Capability header and the rest of capabilities are located at
an offset greater than 0FFh relative to the beginning of PCI compatible configuration space.
31 –24
23 – 16
15 - 8
7 –0
BYTE OFFSET
Next Capability Offset
Cap.
Version
PCI Express Extended Capability ID=0001h
100h
Uncorrectable Error Status Register
104h
Uncorrectable Error Mask Register
108h
Uncorrectable Error Severity Register
10Ch
Correctable Error Status Register
110h
Correctable Error Mask Register
114h
Advanced Error Capabilities and Control Register
118h
Header Log Register
11Ch – 128h
Reserved
12Ch – 13Fh
Next Capability Offset=20Ch
Cap.
Version
PCI Express Extended Capability ID=0002h
140h
Port VC Capability Register 1
144h
VC Arbitration Table
Offset=3
Port VC Capability Register 2
148h
Port VC Status Register
Port VC Control Register
14Ch
Port Arbitration Table
Offset=4
VC Resource Capability Register (0)
150h
VC Resource Control Register (0)
154h
VC Resource Status Register (0)
Reserved
158h
Reserved
15Ch-17Ch
Port Arbitration Table with 128 Phases for VC0
180h – 1BCh
Reserved
1C0h – 1FCh
Reserved
200h – 20Bh
Next Capability Offset=000h
Cap.
Version
PCI Express Extended Capability ID=0004h
20Ch
Reserved
Data Select Register
210h
Data Register
214h
Reserved
Power Budget
Capability Register
218h
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