TM Family Datasheet Page 46 of 77 August 2009 – Re" />
參數(shù)資料
型號: PI7C9X20303ULAZPE
廠商: Pericom
文件頁數(shù): 41/77頁
文件大?。?/td> 0K
描述: IC PCIE PACKET SWITCH 132TQFN
標準包裝: 168
系列: UltraLo™
應用: 封裝開關,3 端口/3 線道
接口: PCI Express
封裝/外殼: 132-VFQFN 雙排裸露焊盤
供應商設備封裝: 132-TQFN-EP(10x10)
包裝: 托盤
安裝類型: 表面貼裝
PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 46 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
17
High Driver Current
RO
It indicates the status of the strapping pin HIDRV. The default value may be
changed by SMBus or auto-loading from EEPROM.
Reset to 0b.
21:18
Driver Transmit
Current
RO
It indicates the status of the strapping pins DTX[3:0]. The default value may
be changed by SMBus or auto-loading from EEPROM.
Reset to 0000b.
25:22
De-emphasis
Transmit
Equalization
RO
It indicates the status of the strapping pins DEQ[3:0]. The default value may
be changed by SMBus or auto-loading from EEPROM.
Reset to 1000b.
27:26
Receive Termination
Adjustment
RO
It indicates the status of the strapping pins RXTRMADJ[1:0]. The default
value may be changed by SMBus or auto-loading from EEPROM.
Reset to 00b.
29:28
Transmit
Termination
Adjustment
RO
It indicates the status of the strapping pins TXTRMADJ[1:0]. The default
value may be changed by SMBus or auto-loading from EEPROM.
Reset to 00b.
31:30
Receiver
Equalization Level
Control
RO
It indicates the status of the strapping pins RXEQCTL[1:0]. The default value
may be changed by SMBus or auto-loading from EEPROM.
Reset to 00b.
7.2.54
XPIP CSR2 – OFFSET B8h (Test Purpose Only)
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Reserved
RO
Reset to 00000030h.
7.2.55
TL CSR – OFFSET BCh
BIT
FUNCTION
TYPE
DESCRIPTION
31:0
Reserved
RO
Reset to 00000004h.
7.2.56
SSID/SSVID CAPABILITY ID REGISTER – OFFSET C0h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
SSID/SSVID
Capabilities ID
RO
Read as 0Dh to indicate that these are SSID/SSVID capability registers.
7.2.57
NEXT ITEM POINTER REGISTER – OFFSET C0h
BIT
FUNCTION
TYPE
DESCRIPTION
15:8
Next Item Pointer
RO
Pointer points to the PCI Express capability register (E0h).
Reset to E0h.
7.2.58
SUBSYSTEM VENDOR ID REGISTER – OFFSET C4h
BIT
FUNCTION
TYPE
DESCRIPTION
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