- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1962 > PI7C9X20303ULAZPE (Pericom)IC PCIE PACKET SWITCH 132TQFN PDF資料下載
參數(shù)資料
| 型號： | PI7C9X20303ULAZPE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 45/77頁 |
| 文件大小： | 0K |
| 描述： | IC PCIE PACKET SWITCH 132TQFN |
| 標(biāo)準(zhǔn)包裝： | 168 |
| 系列： | UltraLo™ |
| 應(yīng)用： | 封裝開關(guān)，3 端口/3 線道 |
| 接口： | PCI Express |
| 封裝/外殼： | 132-VFQFN 雙排裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 132-TQFN-EP（10x10） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁當(dāng)前第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁
PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 5 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
TABLE OF CONTENTS
1
FEATURES.........................................................................................................................................................10
2
GENERAL DESCRIPTION..............................................................................................................................11
3
PIN DESCRIPTION...........................................................................................................................................12
3.1
PCI EXPRESS INTERFACE SIGNALS ....................................................................................................12
3.2
PORT CONFIGURATION SIGNALS .......................................................................................................12
3.3
MISCELLANEOUS SIGNALS..................................................................................................................12
3.4
JTAG BOUNDARY SCAN SIGNALS ......................................................................................................13
3.5
POWER PINS.............................................................................................................................................14
4
PIN ASSIGNMENTS .........................................................................................................................................15
4.1
PIN LIST OF 132-PIN TQFN ......................................................................................................................15
5
FUNCTIONAL DESCRIPTION.......................................................................................................................16
5.1
PHYSICAL LAYER CIRCUIT ..................................................................................................................16
5.2
DATA LINK LAYER (DLL)......................................................................................................................18
5.3
TRANSACTION LAYER RECEIVE BLOCK (TLP DECAPSULATION) ..............................................18
5.4
ROUTING ..................................................................................................................................................18
5.5
TC/VC MAPPING......................................................................................................................................19
5.6
QUEUE.......................................................................................................................................................19
5.6.1
PH ....................................................................................................................................................... 19
5.6.2
PD ....................................................................................................................................................... 19
5.6.3
NPHD ................................................................................................................................................. 19
5.6.4
CPLH .................................................................................................................................................. 19
5.6.5
CPLD .................................................................................................................................................. 19
5.7
TRANSACTION ORDERING...................................................................................................................20
5.8
PORT ARBITRATION ..............................................................................................................................20
5.9
FLOW CONTROL .....................................................................................................................................21
5.10
TRANSATION LAYER TRANSMIT BLOCK (TLP ENCAPSULATION) .............................................21
6
EEPROM INTERFACE AND SYSTEM MANAGEMENT BUS..................................................................22
6.1
EEPROM INTERFACE .............................................................................................................................22
6.1.1
AUTO MODE EERPOM ACCESS ..................................................................................................... 22
6.1.2
EEPROM MODE AT RESET .............................................................................................................. 22
6.1.3
EEPROM SPACE ADDRESS MAP .................................................................................................... 22
6.1.4
MAPPING EEPROM CONTENTS TO CONFIGURATION REGISTERS.......................................... 24
6.2
SMBUS INTERFACE .................................................................................................................................29
7
REGISTER DESCRIPTION .............................................................................................................................30
7.1
REGISTER TYPES ....................................................................................................................................30
7.2
TRANSPARENT MODE CONFIGURATION REGISTERS....................................................................30
7.2.1
VENDOR ID REGISTER – OFFSET 00h ........................................................................................... 32
7.2.2
DEVICE ID REGISTER – OFFSET 00h............................................................................................. 32
7.2.3
COMMAND REGISTER – OFFSET 04h ............................................................................................ 32
7.2.4
PRIMARY STATUS REGISTER – OFFSET 04h................................................................................. 33
7.2.5
REVISION ID REGISTER – OFFSET 08h ......................................................................................... 33
7.2.6
CLASS CODE REGISTER – OFFSET 08h ......................................................................................... 33
7.2.7
CACHE LINE REGISTER – OFFSET 0Ch......................................................................................... 34
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C9X20404GPBNBE | IC PCIE PACKET SWITCH 148LFBGA |
| PI7C9X20404SLCFDE | IC PCIE PACKET SWITCH 128LQFP |
| PI7C9X20505GPBNDE | IC PCIE PACKET SWITCH 256BGA |
| PI7C9X20508GPBNDE | IC PCIE PACKET SWITCH 256BGA |
| PI7C9X440SLBFDE | IC PCIE-TO-USB 2.0 CTRLR 128LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C9X20303ULAZPEX | 功能描述:外圍驅(qū)動器與原件 - PCI 3port 3lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20404GPANBE | 制造商:Pericom Semiconductor Corporation 功能描述:4PORT 4LANE PCIE PACKETSWITCH - Trays |
| PI7C9X20404GPBNBE | 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C9X20404SLCEVB | 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits) |
| PI7C9X20404SLCFDE | 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。