TM Family Datasheet Page 35 of 77 August 2009 – Re" />
參數(shù)資料
型號： PI7C9X20303ULAZPE
廠商： Pericom
文件頁數(shù)： 29/77頁
文件大小： 0K
描述： IC PCIE PACKET SWITCH 132TQFN
標(biāo)準(zhǔn)包裝： 168
系列： UltraLo™
應(yīng)用： 封裝開關(guān)，3 端口/3 線道
接口： PCI Express
封裝/外殼： 132-VFQFN 雙排裸露焊盤
供應(yīng)商設(shè)備封裝： 132-TQFN-EP（10x10）
包裝： 托盤
安裝類型： 表面貼裝
PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 35 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
7.2.13
SECONDARY LATENCY TIMER REGISTER – OFFSET 18h
BIT
FUNCTION
TYPE
DESCRIPTION
31:24
Secondary Latency
Timer
RO
Does not apply to PCI Express. Must be hardwired to 00h.
7.2.14
I/O BASE ADDRESS REGISTER – OFFSET 1Ch
BIT
FUNCTION
TYPE
DESCRIPTION
3:0
32-bit Indicator
RO
Read as 01h to indicate 32-bit I/O addressing.
7:4
I/O Base Address
[15:12]
RW
Defines the bottom address of the I/O address range for the Bridge to
determine when to forward I/O transactions from one interface to the other.
The upper 4 bits correspond to address bits [15:12] and are writable. The
lower 12 bits corresponding to address bits [11:0] are assumed to be 0. The
upper 16 bits corresponding to address bits [31:16] are defined in the I/O base
address upper 16 bits address register.
Reset to 0h.
7.2.15
I/O LIMIT ADDRESS REGISTER – OFFSET 1Ch
BIT
FUNCTION
TYPE
DESCRIPTION
11:8
32-bit Indicator
RO
Read as 01h to indicate 32-bit I/O addressing.
15:12
I/O Limit Address
[15:12]
RW
Defines the top address of the I/O address range for the Bridge to determine
when to forward I/O transactions from one interface to the other. The upper 4
bits correspond to address bits [15:12] and are writable. The lower 12 bits
corresponding to address bits [11:0] are assumed to be FFFh. The upper 16
bits corresponding to address bits [31:16] are defined in the I/O limit address
upper 16 bits address register.
Reset to 0h.
7.2.16
SECONDARY STATUS REGISTER – OFFSET 1Ch
BIT
FUNCTION
TYPE
DESCRIPTION
20:16
Reserved
RO
Reset to 00000b.
21
66MHz Capable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
22
Reserved
RO
Reset to 0b.
23
Fast Back-to-Back
Capable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
24
Master Data Parity
Error
RWC
Set to 1 (by a requester) whenever a Parity error is detected or forwarded on
the secondary side of the port in a Switch.
If the Parity Error Response Enable bit is cleared, this bit is never set.
Reset to 0b.
26:25
DEVSEL_L timing
RO
Does not apply to PCI Express. Must be hardwired to 0b.
27
Signaled Target
Abort
RO
Set to 1 (by a completer) whenever completing a request in the secondary side
using Completer Abort Completion Status.
Reset to 0b.
28
Received Target
Abort
RO
Set to 1 (by a requestor) whenever receiving a Completion with Completer
Abort Completion Status in the secondary side.
Reset to 0b.
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PI7C9X20303ULAZPEX 功能描述:外圍驅(qū)動器與原件 - PCI 3port 3lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20404GPANBE 制造商:Pericom Semiconductor Corporation 功能描述:4PORT 4LANE PCIE PACKETSWITCH - Trays
PI7C9X20404GPBNBE 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe PacketSwitch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C9X20404SLCEVB 制造商:Pericom Semiconductor Corporation 功能描述:PCIE 4 PORT SWITCH EVAL BOARD - Boxed Product (Development Kits)
PI7C9X20404SLCFDE 功能描述:外圍驅(qū)動器與原件 - PCI 4port 4lane PCIe Packet Switch RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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