TM Family Datasheet Page 29 of 77 August 2009 – Re" />
參數(shù)資料
型號(hào): PI7C9X20303ULAZPE
廠商: Pericom
文件頁(yè)數(shù): 22/77頁(yè)
文件大?。?/td> 0K
描述: IC PCIE PACKET SWITCH 132TQFN
標(biāo)準(zhǔn)包裝: 168
系列: UltraLo™
應(yīng)用: 封裝開(kāi)關(guān),3 端口/3 線道
接口: PCI Express
封裝/外殼: 132-VFQFN 雙排裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 132-TQFN-EP(10x10)
包裝: 托盤(pán)
安裝類型: 表面貼裝
PI7C9X20303UL
3Port-3Lane PCI Express Switch
UltraLo
TM Family
Datasheet
Page 29 of 77
August 2009 – Revision 1.1
Pericom Semiconductor
6.2
SMBus INTERFACE
The PI7C9X20303UL provides the System Management Bus (SMBus), a two-wire interface through which a
simple device can communicate with the rest of the system. The SMBus interface on the PI7C9X20303UL is a bi-
directional slave interface. It can receive data from the SMBus master or send data to the master. The interface
allows full access to the configuration registers. A SMBus master, such as the processor or other SMBus devices,
can read or write to every RW configuration register (read/write register). In addition, the RO and HwInt registers
(read-only and hardware initialized registers) that can be auto-loaded by the EEPROM interface can also be read
and written by the SMBus interface. This feature allows increases in the system expandability and flexibility in
system implementation.
Figure 6-1 SMBus Architecture Implementation on PI7C9X20303UL
PI7C9X20303UL
SMBCLK
SMBDATA
Processor
(SMBus Master)
Other SMBus
Devices
The SMBus interface on the PI7C9X20303UL consists of one SMBus clock pin (SMBCLK), a SMBus data pin
(SMBDATA), and 3 SMBus address pins (GPIO[5:7]). The SMBus clock pin provides or receives the clock signal.
The SMBus data pin facilitates the data transmission and reception. Both of the clock and data pins are bi-
directional. The SMBus address pins determine the address to which the PI7C9X20303UL responds to. The SMBus
address pins generate addresses according to the following table:
Table 6-1 SMBus Address Pin Configuration
BIT
SMBus Address
0
GPIO[5]
1
GPIO[6]
2
GPIO[7]
3
1
4
0
5
1
6
1
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