
MFR4200 FlexRay Communication Controller
MFR4200 Data Sheet, Rev. 0
90
Freescale Semiconductor
3.2.3.3.35
Idle Detection Length Register (IDLR)
FlexRay protocol related parameter – gdDynamicSlotIdlePhase
Address 0xAA
Reset
undefined state
This register defines the number of minislots used by the CC for checking the duration of the network idle
time between two consecutive frames in the dynamic segment. This includes the dynamic slot idle phase.
Writing this register is possible only during the configuration state.
The value of IDLR depends on the values of the bit duration register (
Section 3.2.3.3.1, “Bit Duration
Register (BDR)
) and the minislot length register (
Section 3.2.3.3.12, “Minislot Length Register (MSLR)
).
It can be calculated using
Equation 3-9
.
IDLR = ceil( (11 * BDR) / (NMLR * MSLR) ).
Eqn. 3-9
The value in the register must be in the range [1:15].
3.2.3.3.36
Symbol Window Control Register (SWCTRLR)
Address 0x84
Reset
0x0
This register controls the transmission of symbols in a symbol window of a communication cycle. The
register may be modified during the configuration state and during normal operation.
CHB and CHA determine whether a symbol will be transmitted on channel B or channel A, respectively.
1 – Symbol transmission enabled.
15
14
13
12
11
10
9
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
r
r
r
r
r
r
r
r
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
IDL3
IDL2
IDL1
IDL0
r
r
r
r
rw*
rw*
rw*
rw*
Figure 3-48. Idle Detection Length Register
15
14
13
12
11
10
9
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
r
r
r
r
r
r
r
r
7
6
5
4
3
2
1
0
Reserved
CHB
CHA
Reserved
Reserved
Reserved
Reserved
Reserved
r
rw
rw
r
r
r
r
r
Figure 3-49. Symbol Window Control Register