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參數(shù)資料
| 型號： | pentium II |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II processor With On-die Cache Mobile Module Connector 1 (MMC-1)(帶緩存和連接器1的奔II處理器) |
| 中文描述： | 奔騰II處理器芯片上緩存手機(jī)模塊連接器1（MMC管理- 1）（帶緩存和連接器1的奔二處理器） |
| 文件頁數(shù)： | 21/34頁 |
| 文件大?。?/td> | 582K |
| 代理商： | PENTIUM II |
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21
Intel
a
Pentium
a
II Processor With On-die Cache Mobile Module MMC-1
The Stop Grant and the Quick Start clock states are mutually
exclusive. For example a strapping option on signal A15#
chooses which state is entered when the STPCLK# signal is
asserted. Strapping the A15# signal to ground at Reset
enables the Quick Start state. Otherwise, asserting the
STPCLK# signal puts the processor into the Stop Grant
state. The Stop Grant state is useful for SMP platforms and
is not supported on the Pentium II processor with on-die
cache mobile module MMC-1. The Quick Start state is
available on the module and provides a significantly lower
power level. Figure 3 provides an illustration of the clocking
architecture. Performing state transitions not shown in Figure
3 is neither recommended nor supported.
HALT/Grant
Snoop
Normal
State
HS=false
Stop
Grant
Auto
Halt
HS=true
Quick
Start
Sleep
Deep
Sleep
(!STPCLK#
and !HS) or
stop break
STPCLK# and
!QSE and SGA
Snoop
occurs
Snoop
serviced
STPCLK# and
QSE and SGA
(!STPCLK# and !HS)
or RESET#
Snoop
serviced
Snoop
occurs
!STPCLK#
and HS
STPCLK# and
!QSE and SGA
HLT and
halt bus cycle
halt
break
Snoop
serviced
Snoop
occurs
STPCLK# and
QSE and SGA
!STPCLK#
and HS
!SLP# or
RESET#
SLP#
BCLK
stopped
BCLK on
and !QSE
BCLK
stopped
BCLK on
and QSE
Halt break – A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#
HLT – HLT instruction executed
HS – Processor Halt State
QSE – Quick Start State Enabled
SGA – Stop Grant Acknowledge bus cycle issued
Stop break – BINIT#, FLUSH#, RESET#
Intel mobile modules do not support the shaded clock control states
Figure 3. Clock Control States
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