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參數(shù)資料
| 型號： | pentium II |
| 廠商： | Intel Corp. |
| 英文描述： | pentium II processor With On-die Cache Mobile Module Connector 1 (MMC-1)(帶緩存和連接器1的奔II處理器) |
| 中文描述： | 奔騰II處理器芯片上緩存手機模塊連接器1（MMC管理- 1）（帶緩存和連接器1的奔二處理器） |
| 文件頁數(shù)： | 20/34頁 |
| 文件大?。?/td> | 582K |
| 代理商： | PENTIUM II |
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20
Intel
a
Pentium
a
II Processor With On-die Cache Mobile Module MMC-1
allow all host and SDRAM clocks to be generated from the
same clocking architecture on the system electronics. For
complete details about using SDRAM memory and for trace
length guidelines, refer to the
Mobile Pentium II processor /
82443BX PCIset Advanced Platform Recommended Design
and Debug Practices.
Refer to the
Intel
a
440BX PCIset
Datasheet
for details on memory device support,
organization, size, and addressing.
4.3.2
Reset Strap Options
Several strap options on the memory address bus define the
behavior of the module after reset. Other straps are allowed
to override the default settings. Table 12 shows the various
straps and their implementation.
Table 12. Configuration Straps for the 82443DX Host Bridge System Controller
Signal
Function
Module Default Setting
MAB[12]#
Host Frequency
Select
No strap
66-MHz default.
MAB[11]#
In order queue depth
No strap
maximum queue depth is set, i.e. 8.
MAB[10]
Quick Start select
Strapped high on the module for Quick Start mode.
MAB[9]#
AGP disable
Strapped to disable AGP.
MAB[7]#
MM Config
Strapped for MMC-1 compatible mode.
MAB[6]#
Host Bus Buffer Mode
select
Strapped high on the module for mobile PSB buffers.
4.3.3
PCI Interface
The PCI interface of the 82443DX Host Bridge is available at
the connector. The 82443DX Host Bridge supports the PCI
Clockrun protocol for PCI bus power management. In this
protocol, PCI devices assert the CLKRUN# open-drain
signal when they require the use of the PCI interface. Refer
to the
PCI Mobile Design Guide
for complete details on the
PCI Clockrun protocol.
The 82443DX Host Bridge is responsible for arbitrating the
PCI bus. With the MMC-1 connector the 82443DX Host
Bridge can support up to five PCI bus masters. There are
five PCI Request/Grant pairs, REQ[4:0]# and GNT[4:0]#,
available to the manufacturer’s system electronics.
The PCI interface on the connector is 3.3 volts only. All
devices that drive outputs to a 5.0
Vt
nominal V
oh
level are not
supported.
The 82443DX Host Bridge system controller is compliant
with the PCI 2.1 specification, which improves the worst
case PCI bus access latency from earlier PCI specifications.
As detailed in the PCI specification, the 82443DX Host
Bridge supports only Mechanism #1 for accessing PCI
configuration space. This implies that signals AD[31:11] are
available for PCI IDSEL signals. However, since the
82443DX Host Bridge is always device #0, AD11 will never
be asserted during PCI configuration cycles as an IDSEL.
The 82443DX reserves AD12 for the AGPbus, which is not
supported by the MMC-1 connector. Thus, AD13 is the first
available address line usable as an IDSEL. AD18 should be
used by the PIIX4E/M.
4.3.4
AGP Feature Set
The Intel MMC-1 connector family does not support the AGP
graphics port interface. For AGP information, refer to the
Intel
a
Pentium
a
Processor Mobile Module: Mobile Module
Connector 2 (MMC-2).
4.4
Power Management
4.4.1
Clock Control Architecture
The Pentium II processor with on-die cache mobile module’s
clock control architecture is optimal for notebook designs.
The clock control architecture consists of seven different
clock states: Normal, Stop Grant, Auto Halt, Quick Start,
HALT/Grant Snoop, Sleep, and Deep Sleep. The Auto Halt
state provides a low power clock state that can be controlled
through the software execution of the HLT instruction. The
Quick Start state provides a low power, low exit latency clock
state that can be used for hardware controlled “idle”
computer states. The Deep Sleep state provides an
extremely low power state that can be used for Power-on-
Suspend states, which is an alternative to shutting off the
processor’s power. The exit latency of the Deep Sleep state
has been reduced to 30 microseconds. The Stop Grant and
Sleep states are not available on the Pentium II processor
with on-die cache mobile module as these states are
intended for desktop or server systems.
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