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| 型號(hào)： | PCI9060ES |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| 中文描述： | 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng) |
| 文件頁(yè)數(shù)： | 73/192頁(yè) |
| 文件大小： | 1551K |
| 代理商： | PCI9060ES |
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SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 64
Version 1.02
4.4.3 (MARBR; PCI:08h or ACh, LOC:88h or 12Ch) Mode/Arbitration Register
Table 4-35. (MARBR; PCI:08h or ACh, LOC:88h or 12Ch) Mode/Arbitration Register
Field
Description
Read
Write
Value after Reset
7:0
Local Bus Latency Timer. Number of local bus clock cycles before negating HOLD
and releasing the local bus. This timer is also used with bit 27 to delay BREQ input
to give up the local bus only when this timer expires.
Yes
Yes
00
15:8
Local Bus Pause Timer. Number of local bus clock cycles before reasserting HOLD
after releasing the local bus.
Note:
Applicable only to DMA operation.
Yes
Yes
00
16
Local Bus Latency Timer Enable. Value of 1 enables latency timer.
Yes
Yes
0
17
Local Bus Pause Timer Enable. Value of 1 enables pause timer.
Yes
Yes
0
18
Local Bus BREQ Enable. Value of 1 enables local bus BREQ input. When the
BREQ input is active, PCI 9080 negates HOLD and releases the local bus.
Yes
Yes
0
20:19
DMA Channel Priority. Value of 00 indicates a rotational priority scheme. Value of
01 indicates Channel 0 has priority. Value of 10 indicates Channel 1 has priority.
Value of 11 is reserved.
Yes
Yes
0
21
Local Bus Direct Slave Give up Bus Mode. When set to 1, PCI 9080 negates HOLD
and releases the local bus when the Direct Slave write FIFO becomes empty during
a Direct Slave write or when the Direct Slave read FIFO becomes full during a
Direct Slave read.
Yes
Yes
1
22
Direct Slave LLOCKo# Enable. Value of 1 enables PCI Direct Slave locked
sequences. Value of 0 disables Direct Slave locked sequences.
Yes
Yes
0
23
PCI Request Mode. Value of 1 causes PCI 9080 to negate REQ when it asserts
FRAME during a master cycle. Value of 0 causes PCI 9080 to leave REQ asserted
for the entire bus master cycle.
Yes
Yes
0
24
PCI Rev 2.1 Mode. When set to 1, PCI 9080 operates in Delayed Transaction mode
for Direct Slave Reads. PCI 9080 issues a RETRY and prefetches the read data.
Yes
Yes
0
25
PCI Read No Write Mode. Value of 1 forces a retry on writes if read is pending.
Value of 0 allows writes to occur while read is pending.
Yes
Yes
0
26
PCI Read with Write Flush Mode. Value of 1 submits a request to flush a pending
read cycle if a write cycle is detected. Value of 0 submits a request to not effect
pending reads when a write cycle occurs (PCI v2.1 compatible).
Yes
Yes
0
27
Gate the Local Bus Latency Timer with BREQ. If this bit is set to 0, PCI 9080 gives
up the local bus during Direct Slave or DMA transfer after the current cycle (if
enabled and BREQ is sampled). If this bit is set to 1, PCI 9080 gives up the local
bus only (if BREQ is sampled) and the Local Bus Latency Timer is enabled and
expired during Direct Slave or DMA transfer.
Yes
Yes
0
28
PCI Read No Flush Mode. Value of 1 submits request to not flush the read FIFO
if PCI read cycle completes (Read Ahead mode).
Value of 0 submits request to flush read FIFO if PCI read cycle completes.
Yes
Yes
0
29
If set to 0, reads from the PCI Configuration Register address 00h and returns the
Device ID and Vendor ID. If set to 1, reads from the PCI Configuration Register
address 00h and returns the Subsystem ID and Subsystem Vendor ID.
Yes
Yes
0
31:30
Reserved.
Yes
No
0
相關(guān)PDF資料 |
PDF描述 |
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| PCI9060SD | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI950PT | PC Card Support |
| PCI9656-AC66BI | Controller Miscellaneous - Datasheet Reference |
| PCIB40 | PC(ISA)BUS I/O CARD |
| PCICLOCKGEN_R001 | AMD Alchemy? Solutions Au1500? PCI Clock Generation? |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI9060ESF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9060ESREV1 | 制造商:PLX Technology 功能描述: |
| PCI9060SD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI9060SD-1AF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9080 | 制造商:PLX 制造商全稱:PLX 功能描述:I2O Compatible PCI Bus Master I/O Accelerator Chip |
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