
PCI 9080
TABLE OF CONTENTS
PLX Technology, Inc., 1997
Page iii
Version 1.01
TABLE OF CONTENTS
1.
GENERAL DESCRIPTION ..............................................................................................................................................1
1.1
APPLICATIONS FOR THE PCI 9080.......................................................................................................................2
1.1.1
PCI Adapter Cards..............................................................................................................................................................2
1.1.2
Embedded Systems............................................................................................................................................................2
1.2
MAJOR FEATURES..................................................................................................................................................3
1.3
COMPATIBILITY OF PCI 9080 WITH PCI 9060, 9060ES, AND 9060SD................................................................4
1.3.1
Pin Compatibility.................................................................................................................................................................4
1.3.2
Register Compatibility.........................................................................................................................................................4
1.4
COMPARISON OF PCI 9060, PCI 9060ES, PCI 9060SD, AND PCI 9080..............................................................5
2.
BUS OPERATION............................................................................................................................................................6
2.1
PCI BUS CYCLES.....................................................................................................................................................6
2.1.1
PCI Target Command Codes..............................................................................................................................................6
2.1.2
PCI Master Command Codes.............................................................................................................................................6
2.1.2.1
DMA Master Command Codes.......................................................................................................................................6
2.1.2.2
Direct Local to PCI Command Codes.............................................................................................................................6
2.1.3
PCI Arbitration ....................................................................................................................................................................6
2.2
LOCAL BUS CYCLES...............................................................................................................................................7
2.2.1
Local Bus Arbitration...........................................................................................................................................................7
2.2.2
Local Bus Direct Master......................................................................................................................................................7
2.2.3
Local Bus Direct Slave........................................................................................................................................................7
2.2.3.1
Ready/Wait State Control ...............................................................................................................................................7
2.2.3.1.1
Wait State—Local Side.............................................................................................................................................7
2.2.3.1.2
Wait State—PCI Side ...............................................................................................................................................8
2.2.3.2
Burst Mode and Continuous Burst Mode (Bterm “Burst Terminate” Mode).....................................................................8
2.2.3.2.1
Burst Mode ...............................................................................................................................................................8
2.2.3.2.2
Continuous Burst Mode (Bterm “Burst Terminate” Mode).........................................................................................8
2.2.3.2.3
Partial Lword Accesses ............................................................................................................................................9
2.2.3.3
Recovery States .............................................................................................................................................................9
2.2.3.4
Local Bus Read Accesses..............................................................................................................................................9
2.2.3.5
Local Bus Write Accesses ..............................................................................................................................................9
2.2.3.6
Direct Slave Write Accesses—8- and 16-Bit Buses........................................................................................................9
2.2.3.7
Local Bus Data Parity .....................................................................................................................................................9
2.2.3.8
Local Bus Little/Big Endian.............................................................................................................................................9
2.2.3.8.1
32 Bit Local Bus—Big Endian Mode.........................................................................................................................9
2.2.3.8.2
16 Bit Local Bus—Big Endian Mode.......................................................................................................................10
2.2.3.8.3
8 Bit Local Bus—Big Endian Mode.........................................................................................................................10