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參數(shù)資料
| 型號(hào)： | PCI9060ES |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| 中文描述： | 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng) |
| 文件頁(yè)數(shù)： | 6/192頁(yè) |
| 文件大小： | 1551K |
| 代理商： | PCI9060ES |
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PCI 9080
TABLE OF CONTENTS
PLX Technology, Inc., 1997
Page vii
Version 1.01
4.3.23
(PCIMLR; PCI:3Fh, LOC:3Fh) PCI Max_Lat Register ......................................................................................................62
4.4
LOCAL CONFIGURATION REGISTERS ...............................................................................................................63
4.4.1
(LAS0RR; PCI:00h, LOC:80h) Local Address Space 0 Range Register for PCI to Local Bus..........................................63
4.4.2
(LAS0BA; PCI:04h, LOC:84h) Local Address Space 0 Local Base Address (Remap) Register.......................................63
4.4.3
(MARBR; PCI:08h or ACh, LOC:88h or 12Ch) Mode/Arbitration Register........................................................................64
4.4.4
(BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor Register...............................................................................65
4.4.5
(EROMRR; PCI:10h, LOC:90h) Expansion ROM Range Register ...................................................................................66
4.4.6
(EROMBA; PCI:14h, LOC:94h) Expansion ROM Local Base Address (Remap) Register and BREQo Control...............66
4.4.7
(LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion ROM Bus Region Descriptor Register.........................67
4.4.8
(DMRR; PCI:1Ch, LOC:9Ch) Local Range Register for Direct Master to PCI...................................................................68
4.4.9
(DMLBAM; PCI:20h, LOC:A0h) Local Bus Base Address Register for Direct Master to PCI Memory..............................68
4.4.10
(DMLBAI; PCI:24h, LOC:A4h) Local Base Address Register for Direct Master to PCI IO/CFG........................................68
4.4.11
(DMPBAM; PCI:28h, LOC:A8h) PCI Base Address (Remap) Register for Direct Master to PCI Memory ........................69
4.4.12
(DMCFGA; PCI:2Ch, LOC:ACh) PCI Configuration Address Register for Direct Master to PCI IO/CFG..........................70
4.4.13
(LAS1RR; PCI:F0h, LOC:170h) Local Address Space 1 Range Register for PCI to Local Bus........................................70
4.4.14
(LAS1BA; PCI:F4h, LOC:174h) Local Address Space 1 Local Base Address (Remap) Register.....................................71
4.4.15
(LBRD1; PCI:F8h, LOC:178h) Local Address Space 1 Bus Region Descriptor Register..................................................71
4.5
RUNTIME REGISTERS..........................................................................................................................................72
4.5.1
(MBOX0; PCI:40h or 78h, LOC:C0h) Mailbox Register 0 .................................................................................................72
4.5.2
(MBOX1; PCI:44h or 7Ch, LOC:C4h) Mailbox Register 1.................................................................................................72
4.5.3
(MBOX2; PCI:48h, LOC:C8h) Mailbox Register 2 ............................................................................................................72
4.5.4
(MBOX3; PCI:4Ch, LOC:CCh) Mailbox Register 3 ...........................................................................................................72
4.5.5
(MBOX4; PCI:50h, LOC:D0h) Mailbox Register 4 ............................................................................................................72
4.5.6
(MBOX5; PCI:54h, LOC:D4h) Mailbox Register 5 ............................................................................................................73
4.5.7
(MBOX6; PCI:58h, LOC:D8h) Mailbox Register 6 ............................................................................................................73
4.5.8
(MBOX7; PCI:5Ch, LOC:DCh) Mailbox Register 7 ...........................................................................................................73
4.5.9
(P2LDBELL; PCI:60h, LOC:E0h) PCI to Local Doorbell Register.....................................................................................73
4.5.10
(L2PDBELL; PCI:64h, LOC:E4h) Local to PCI Doorbell Register.....................................................................................73
4.5.11
(INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status Register......................................................................................74
4.5.12
(CNTRL; PCI:6Ch, LOC:ECh) Serial EEPROM Control, PCI Command Codes, User I/O Control,
Init Control Register..........................................................................................................................................................76
4.5.13
(PCIHIDR; PCI:70h, LOC:F0h) PCI Permanent Configuration ID Register.......................................................................77
4.5.14
(PCIHREV; PCI:74h, LOC:F4h) PCI Permanent Revision ID Register.............................................................................77
4.6
DMA REGISTERS...................................................................................................................................................78
4.6.1
(DMAMODE0; PCI:80h, LOC:100h) DMA Channel 0 Mode Register...............................................................................78
4.6.2
(DMAPADR0; PCI:84h, LOC:104h) DMA Channel 0 PCI Address Register.....................................................................79
4.6.3
(DMALADR0; PCI:88h, LOC:108h) DMA Channel 0 Local Address Register...................................................................79
4.6.4
(DMASIZ0; PCI:8Ch, LOC:10Ch) DMA Channel 0 Transfer Size (Bytes) Register ..........................................................79
4.6.5
(DMADPR0; PCI:90h, LOC:110h) DMA Channel 0 Descriptor Pointer Register...............................................................79
4.6.6
(DMAMODE1; PCI:94h, LOC:114h) DMA Channel 1 Mode Register...............................................................................80
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI9060ESF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9060ESREV1 | 制造商:PLX Technology 功能描述: |
| PCI9060SD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI9060SD-1AF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9080 | 制造商:PLX 制造商全稱:PLX 功能描述:I2O Compatible PCI Bus Master I/O Accelerator Chip |
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