參數(shù)資料
型號(hào)： PCI9060ES
廠商： Electronic Theatre Controls, Inc.
英文描述： 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
中文描述： 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng)
文件頁(yè)數(shù)： 48/192頁(yè)
文件大?。?/td> 1551K
代理商： PCI9060ES
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SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 39
Version 1.02
specifies that the number of message frames allocated
should be less than or equal to the number of entries in
a FIFO. (Refer to Figure 3-24 for additional information.)
Each inbound MFA is specified by I
2
O as the offset from
the start of shared local (IOP) memory region 0 to the
start of the message frame. Each outbound MFA is
specified as the offset from Host memory location
0x00000000h to the start of the message frame in
shared Host memory. Since the MFA is an actual
address, the message frames need not be contiguous.
IOP allocates and initializes inbound message frames in
shared IOP memory using any suitable memory
allocation technique. Host allocates and initializes
outbound message frames in shared Host memory using
any suitable memory allocation technique. Message
frames are a minimum of 64 bytes in length.
I
2
O uses a “push” (write preferred) memory model. That
means that the IOP will write messages and data to the
shared Host memory, and the Host will write messages
and data to shared IOP memory. Software should make
use of burst and DMA transfers whenever possible to
ensure efficient use of the PCI bus for message passing.
Additional
implementation may be found in the I
2
O Architecture
Specification v1.5
information
on
message
passing
3.13.4 Inbound Free List FIFO
The local processor allocates inbound message frames
in its shared memory and can place the address of a
free (available) message frame into the Inbound Free
List FIFO by writing its MFA into the FIFO location
pointed to by the Queue Base Register + Inbound Free
Head Pointer Register. The local processor must then
increment the Inbound Free Head Pointer Register.
A PCI master (Host or another IOP) can obtain the MFA
of a free message frame by reading the Inbound Queue
Port Address (40h of the first PCI Memory Base Address
Register). If FIFO is empty (no free inbound message
frames are currently available, head and tail pointers are
equal), the MU returns a value of -1 (FFFFFFFFh). If
FIFO is not empty (head and tail pointers are not equal),
the MU reads the MFA pointed to by the Queue Base
Register + Inbound Free Tail Pointer Register, returns its
value and increments the Inbound Free Tail Pointer
Register. If Inbound Free Queue is not empty, and
queue prefetching is enabled (QSR Register bit 3), the
next entry in the FIFO is read from the local bus into a
prefetch register. The prefetch register then provides the
data for the next PCI read from this queue, thus reducing
the number of PCI wait states.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCI9060ESF 功能描述:數(shù)字總線開(kāi)關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開(kāi)關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel
PCI9060ESREV1 制造商:PLX Technology 功能描述:
PCI9060SD 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
PCI9060SD-1AF 功能描述:數(shù)字總線開(kāi)關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開(kāi)關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel
PCI9080 制造商:PLX 制造商全稱(chēng):PLX 功能描述:I2O Compatible PCI Bus Master I/O Accelerator Chip
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