- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄367822 > PCI9060ES (Electronic Theatre Controls, Inc.) 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS PDF資料下載
參數(shù)資料
| 型號(hào)： | PCI9060ES |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| 中文描述： | 12O兼容的PCI總線主控接口芯片的適配器和嵌入式系統(tǒng) |
| 文件頁(yè)數(shù)： | 36/192頁(yè) |
| 文件大?。?/td> | 1551K |
| 代理商： | PCI9060ES |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)當(dāng)前第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)
SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 27
Version 1.02
If timer expires and PCI 9080 has not received LHOLDA,
PCI 9080 asserts BREQo. External bus logic can use
this as a signal to perform backoff.
A backoff cycle is device/bus architecture dependent.
External logic (arbiter) can assert the necessary signals
to cause the local master to release the local bus
(backoff). After backing off the local master, it can grant
the bus to the PCI 9080 (by asserting LHOLDA).
Once BREQo is asserted, READYo# for the current data
cycle will never be asserted (the local bus master must
perform backoff). When the PCI 9080 detects LHOLDA,
It proceeds with the PCI master to local bus access.
When this access is complete and the PCI 9080
releases the local bus, the external logic can release
backoff and the local master can resume the cycle that
was interrupted by the backoff cycle. The write FIFO of
the PCI 9080 retains all the data it has acknowledged
(i.e. the last data for which READYo# was asserted).
After the backoff condition ends, the local master
restarts the last cycle with ADS#. For writes, the data
following this ADS# should be the data that was not
acknowledged by the PCI 9080 prior to the backoff cycle
(for instance, the last data for which there was no
READYo# asserted).
If a PCI read cycle is completed when the local bus is
backed off, the local bus master receives that data if
local master restarts the same last cycle. (Data is not
read twice). A new read is performed, if the resumed
local bus cycle is not the same as the backed off cycle.
3.6.2.3.2 Software/Hardware Solution for Systems
without Backoff Capability
For adapters that do not support backoff, a possible
deadlock solution is as follows.
PCI host software, external local bus hardware, general
purpose output USERO and general purpose input
(USERI) can be used by PCI host software to prevent
deadlock. USERO can be set to request that the external
arbiter not grant the bus to any local bus master except
the PCI 9080. A status output from the local arbiter can
be connected to general purpose input USERI to
indicate that no local bus master owns the local bus. The
input can be read by the PCI host to determine that no
local bus master currently owns the local bus. PCI host
can then perform a direct slave access. When the host is
done, it clears USERO. For devices that support
preempt, USERO can be used to preempt the current
bus master device. The current local bus master device
completes its current cycle and gives up the local bus
(de-asserts LHOLD).
3.6.2.3.3 Software Solutions to Deadlock
PCI host software and local bus software can use a
combination of mailbox registers, doorbell registers,
interrupts, direct local to PCI accesses and direct PCI to
local accesses to avoid deadlock.
3.6.2.4 Direct Slave Lock
PCI 9080 supports direct PCI to local bus exclusive
accesses (locked atomic operations). A PCI locked
operation to local bus results in the entire address space
0, space 1 and expansion ROM space being locked until
they are released by the PCI bus master. PCI 9080
asserts LLOCKo# during the first clock of an atomic
operation (address cycle) and de-asserts it a minimum of
one clock, following the last bus access for the atomic
operation. LLOCKo# is de-asserted after the PCI 9080
detects PCI FRAME# and PCI LOCK# de-asserted at
the same time. Refer to the timing diagrams in Section 8,
“Timing Diagrams.” Locked operations are enabled or
disabled with the Local Bus Region Descriptor Register
for PCI to local accesses.
It is the responsibility of external arbitration logic to
monitor the LLOCKo# pin and enforce the meaning for
an atomic operation. For example, if a local master
initiates a locked operation, the local arbiter may choose
to not grant use of the local bus to other masters until
the locked operation is complete.
3.6.3 Direct Slave Priority
Direct Slave accesses have higher priority than DMA
accesses.
Direct Slave accesses preempt DMA transfers. When
the PCI 9080 DMA controller owns the local bus, its
LHOLD output and LHOLDA input are asserted and its
LDSHOLD output is de-asserted. When a Direct Slave
access occurs, PCI 9080 gives up the local bus within
two Lword transfers by de-asserting LHOLD and floating
its local bus outputs. After the PCI 9080 samples its
LHOLDA input de-asserted, it requests the local bus for
a Direct Slave transfer by asserting LHOLD and
LDSHOLD. When the PCI 9080 receives LHOLDA, it
drives the bus and performs the Direct Slave transfer.
Upon completion of the Direct Slave transfer, PCI 9080
gives up the local bus by de-asserting both LHOLD and
LDSHOLD and floating its local bus outputs. After the
PCI 9080 samples its LHOLDA de-asserted and its local
pause timer is zero, it requests the local bus for a DMA
transfer by re-asserting LHOLD. When it receives
LHOLDA, it drives the bus and continues with the DMA
transfer.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCI9060SD | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI950PT | PC Card Support |
| PCI9656-AC66BI | Controller Miscellaneous - Datasheet Reference |
| PCIB40 | PC(ISA)BUS I/O CARD |
| PCICLOCKGEN_R001 | AMD Alchemy? Solutions Au1500? PCI Clock Generation? |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCI9060ESF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9060ESREV1 | 制造商:PLX Technology 功能描述: |
| PCI9060SD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS |
| PCI9060SD-1AF | 功能描述:數(shù)字總線開關(guān) IC PCI Bus Interface RoHS:否 制造商:Texas Instruments 開關(guān)數(shù)量:24 傳播延遲時(shí)間:0.25 ns 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:TSSOP-56 封裝:Reel |
| PCI9080 | 制造商:PLX 制造商全稱:PLX 功能描述:I2O Compatible PCI Bus Master I/O Accelerator Chip |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。