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參數(shù)資料
| 型號： | PCF8548 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 65 x 102 pixels matrix LCD driver |
| 中文描述： | 65 × 102像素矩陣LCD驅(qū)動器 |
| 文件頁數(shù)： | 6/40頁 |
| 文件大小： | 206K |
| 代理商： | PCF8548 |
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1999 Aug 16
6
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
PCF8548
8
BLOCK DIAGRAM FUNCTIONS
8.1
Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC input must be connected to V
DD1
. An external
clock signal (if used), is connected to this input.
8.2
I
2
C-bus interface
The I
2
C-bus interface receives and executes the
commands sent via the I
2
C-bus. It also receives RAM data
and sends it to the RAM.
8.3
Display control logic
The display control logic generates the control signals to
read from the RAM via the 102 bits parallel port. It also
generates the control signals for the row and column
drivers.
8.4
Display Data RAM (DDRAM)
The PCF8548 contains a 65
×
102 bit static RAM which
stores the display data. The RAM is divided into 8 banks of
102 bytes and 1 bank of 102 bits [(8
×
8 + 1)
×
102 bits].
During RAM access, data is transferred to the RAM via the
I
2
C-bus interface. There is a direct correspondence
between the X address and column output number.
8.5
Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the I
2
C-bus.
8.6
LCD row and column drivers
The PCF8548 contains 65 row and 102 column drivers,
which connect the appropriate LCD bias voltages to the
display in accordance with the data to be displayed.
Figure 2showstypicalwaveforms.Unusedoutputsshould
be left unconnected.
9
INITIALIZATION
Immediately following Power-on, all internal registers and
the RAM content are undefined. A reset pulse must first be
applied.
Reset is accomplished by applying an external RES pulse
(active LOW). When reset occurs within the specified time
allinternal registers areinitialized, however the RAMisstill
undefined. The state after reset is described in
Section 12.1.
The RES input must be
≤
0.3 V
DD
when V
DD
reaches
V
DD(min)
(or higher) within a maximum time t
VHRL
after V
DD
goes HIGH (see Fig.17).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCF8549 | 65 x 102 pixels matrix LCD driver |
| PCF8549U | 65 x 102 pixels matrix LCD driver |
| PCF8558 | Universal LCD driver for small graphic panels(應(yīng)用于小型圖形面板的通用LCD驅(qū)動器) |
| PCF8558U | Universal LCD driver for small graphic panels |
| PCF8563 | Real-time clock/calendar(實(shí)時時鐘/日歷) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCF8548U/2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver |
| PCF8548U/9 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver |
| PCF8549 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver |
| PCF8549U | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver |
| PCF8549U/2 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver |
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