參數(shù)資料
型號(hào)： PCF8548
廠商： NXP Semiconductors N.V.
英文描述： 65 x 102 pixels matrix LCD driver
中文描述： 65 × 102像素矩陣LCD驅(qū)動(dòng)器
文件頁(yè)數(shù)： 5/40頁(yè)
文件大?。?/td> 206K
代理商： PCF8548
1999 Aug 16
5
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
PCF8548
7
PIN FUNCTIONS
7.1
R0 to R64: row driver outputs
These pads output the row signals.
7.2
C0 to C101: column driver outputs
These pads output the column signals.
7.3
V
SS1
and V
SS2
: negative power supply rails
V
SS2
is related to V
DD2
and V
DD3
and V
SS1
is related to
V
DD1
.
7.4
V
DD1
to V
DD3
: positive power supply rails
V
DD2
and V
DD3
are the supply voltages for the internal
voltage generator. Both have to be at the same voltage
and must be connected together outside of the chip. If the
internal voltage generator is not used, they should both be
connected to power or to the V
DD1
pad.
V
DD1
is used as the power supply for the rest of the chip.
This voltage can be a different voltage than V
DD2
and
V
DD3
.
7.5
V
LCDIN
: LCD power supply
Internally generated positive power supply for the liquid
crystal display. An external LCD supply voltage can be
supplied using the V
LCDIN
pad. In this case, V
LCDOUT
has
to be connected to ground, and the internal voltage
generator has to be programmed to zero. If the PCF8548
is in power-down mode, the external LCD supply voltage
must be switched off.
7.6
V
LCDOUT
: LCD power supply
Positive power supply for the liquid crystal display. If the
internal voltage generator is used, the two supply rails
V
LCDIN
and V
LCDOUT
must be connected together and an
external capacitor must be connected (see Fig.19).
7.7
V
LCDSENSE
: voltage multiplier regulation input
(V
LCD
)
V
LCDSENSE
is the input voltage for the internal voltage
multiplier regulation.
If the internal voltage generator is used then V
LCDSENSE
must be connected to V
LCDOUT
. If an external supply
voltage is used then V
LCDSENSE
must be connected to
ground.
7.8
T1 to T12: test pads
T1 and T3 to T7 must be connected to V
SS1
. T8 must be
connected to V
DD1
. T2 and T9 to T12 must be left
open-circuit; not accessible to user.
7.9
SDAIN and SDAOUT: I
2
C-bus data lines
Serial data and acknowledge lines for the I
2
C-bus.
By connecting SDAIN to SDAOUT, the SDA line becomes
fully I
2
C-bus compatible. Having the acknowledge output
(SDAOUT) separated from the serial data line is
advantageous in Chip-On-Glass (COG) applications.
In COG applications where the track resistance from the
SDAOUT pad to the system SDA line can be significant, a
potential divider is generated by the bus pull-up resistor
and the Indium Tin Oxide (ITO) track resistance. It is
possible that during the acknowledge cycle the PCF8548
will not be able to create a valid logic 0 level. By splitting
the SDA input from the output the device could be used in
a mode that ignores the acknowledge bit. In COG
applications where the acknowledge cycle is required, it is
necessary to minimize the track resistance from the
SDACK pad to the system SDA line to guarantee a valid
LOW level.
7.10
SCL: I
2
C-bus clock signal
I
2
C-bus serial clock signal input.
7.11
SA0: slave address
Two different slave addresses can be selected using the
SA0 pad. This allows two PCF8548 LCD drivers to be
connected to the same I
2
C-bus.
7.12
OSC: oscillator
When the on-chip oscillator is used this input must be
connected to V
DD1
. An external clock signal, if used, is
connected to this input.
7.13
RES: reset
This signal is used to reset the device. The signal is active
LOW.
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