參數(shù)資料
型號: PCF8548
廠商: NXP Semiconductors N.V.
英文描述: 65 x 102 pixels matrix LCD driver
中文描述: 65 × 102像素矩陣LCD驅(qū)動器
文件頁數(shù): 23/40頁
文件大?。?/td> 206K
代理商: PCF8548
1999 Aug 16
23
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
PCF8548
Notes
1.
2.
3.
4.
5.
6.
The maximum possible V
LCD
voltage that can be generated is dependent on voltage, temperature and (display) load.
Internal clock.
When f
sclk
= 0 there is no I
2
C-bus clock.
Power-down mode. During power-down all static currents are switched off.
If external V
LCD
, the display load current is not transmitted to I
DD
.
Tolerance depends on the temperature; (typically zero at T
amb
= 27
°
C), maximum tolerance values are measured
at the temperature range limit.
For TC0 to TC3.
7.
I
DD(tot)
total supply current
with internal V
LCD
generation;
V
DD1
= 2.8 V; V
LCD
= 7.6 V;
f
sclk
= 0; T
amb
= 25
°
C; no
display load; 4
×
charge pump;
notes 2 and 3
(Power-down mode) with
internal or external V
LCD
generation; note 4
V
DD1
= 2.8 V; V
LCD
= 7.6 V;
f
sclk
= 0; T
amb
= 25
°
C; no
display load; notes 2, 3 and 5
200
350
μ
A
1.5
10
μ
A
I
LCDIN
supply current from
external V
LCD
30
μ
A
Logic
V
IL
V
IH
I
L
Column and row outputs
LOW-level input voltage
HIGH-level input voltage
leakage current
V
SS1
0.7V
DD1
1
0.3V
DD1
V
DD1
+1
V
V
μ
A
V
i
= V
DD1
or V
SS1
R
row
row output resistance
R0 to R64
V
DD1
to V
DD3
= 5.0 V;
V
LCD
= 7.6 V; I
L
= 10
μ
A;
outputs tested one at a time
V
LCD
= 7.6 V
12
20
k
R
col
column output
resistance C0 to C101
column bias tolerance
C0 to C101
row bias tolerance
R0 to R64
12
20
k
V
bias(col)
100
0
+
100
mV
V
bias(row)
100
0
+
100
mV
LCD supply voltage generator
V
LCD
V
LCD
tolerance
internally generated
V
DD1
= 2.8 V; V
LCD
= 7.6 V;
f
sclk
= 0; T
amb
= 25
°
C;
no display load;
notes 2, 3 6 and 7
00
01
10
11
300
0
+
300
mV
TC
temperature coefficient
0.0
×
10
3
0.76
×
10
3
1.05
×
10
3
2.10
×
10
3
1/
°
C
1/
°
C
1/
°
C
1/
°
C
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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