參數(shù)資料
型號(hào)： PCF8548
廠商： NXP Semiconductors N.V.
英文描述： 65 x 102 pixels matrix LCD driver
中文描述： 65 × 102像素矩陣LCD驅(qū)動(dòng)器
文件頁數(shù)： 18/40頁
文件大?。?/td> 206K
代理商： PCF8548
1999 Aug 16
18
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
PCF8548
12.2
Function set
12.2.1
P
OWER
-D
OWN
(PD)
All LCD outputs at V
SS
(display off)
Bias generator and V
LCD
generator off
Oscillator off (external clock possible)
V
LCD
can be disconnected
RAM contents not cleared (RAM data can be written)
V
LCD
output is discharged to V
SS
.
12.2.2
V
When V = 0, the horizontal addressing is selected.
The data is written to the RAM as shown in Fig.4. When
V = 1, the vertical addressing is selected. The data is
written to the RAM as shown in Fig.5.
12.2.3
H
When H = 0 the commands ‘display control’, ‘set HV-gen
stages’, ‘set Y address’ and ‘set X address’ can be
performed. When H = 1 the other commands can be
executed. The commands ‘write data’ and ‘function set’
can be executed in both cases.
12.2.4
MX
When MX = 0, the display RAM is written from left to right
(X = 0 is on the left side of the display, X = 100 is on the
right side of the display). When MX = 1 the display RAM is
written from right to left (X = 0 is on the right side of the
display, X = 100 is on the left side of the display).
Thus, if a horizontally mirroring of the display is desired the
RAM must first be rewritten.
12.2.5
MY
When MY = 1, the display is mirrored vertically.
A change of this bit has an immediate effect on the display.
12.3
Display control
12.3.1
D
AND
E
The bits D and E select the display mode (see Table 2).
12.4
Display configuration
12.4.1
TRS
Bit TRS enables the top row pad blocks to be mirrored.
This is used to enable flexibility in the wiring of the row
lines from the PCF8548 to the LCD cell (e.g. COG or TCP
wiring). When TRS = 0 rows 19 to 32 and rows 51 to 64
are organized as illustrated in Fig.22. When TRS = 1 rows
19 to 32 and rows 51 to 64 are mirrored and organized as
illustrated in Fig.23.
12.4.2
BRS
Bit BRS enables the bottom row pad blocks to be mirrored.
This is used to enable flexibility in the wiring of the row
lines from the PCF8548 to the LCD cell (e.g. COG or TCP
wiring). When BRS = 0 rows 0 to 18 and rows 33 to 50 are
organized as illustrated in Fig.22. When BRS = 1 rows
0 to 18 and rows 33 to 50 are mirrored and organized as
illustrated in Fig.23.
12.5
Set Yaddress of RAM
Y[3 : 0] defines the Y address vector address of the RAM.
Table 3
X and Y address ranges
Note
1.
In bank 8 only the MSB is accessed.
Y
3
0
0
0
0
0
0
0
0
1
Y
2
0
0
0
0
1
1
1
1
0
Y
1
0
0
1
1
0
0
1
1
0
Y
0
0
1
0
1
0
1
0
1
0
CONTENT
ALLOWED X RANGE
bank 0 (display RAM)
bank 1 (display RAM)
bank 2 (display RAM)
bank 3 (display RAM)
bank 4 (display RAM)
bank 5 (display RAM)
bank 6 (display RAM)
bank 7 (display RAM)
bank 8 (display RAM); note 1
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
0 to 101
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PCF8548U/2 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver
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PCF8549U 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver
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