參數(shù)資料
型號: PCF8548
廠商: NXP Semiconductors N.V.
英文描述: 65 x 102 pixels matrix LCD driver
中文描述: 65 × 102像素矩陣LCD驅(qū)動器
文件頁數(shù): 2/40頁
文件大?。?/td> 206K
代理商: PCF8548
1999 Aug 16
2
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
PCF8548
CONTENTS
1
2
3
3.1
4
5
6
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
FEATURES
APPLICATIONS
GENERAL DESCRIPTION
Packages
ORDERING INFORMATION
BLOCK DIAGRAM
PINNING
PIN FUNCTIONS
R0 to R64: row driver outputs
C0 to C101: column driver outputs
V
SS1
and V
SS2
: negative power supply rails
V
DD1
to V
DD3
: positive power supply rails
V
LCDIN
: LCD power supply
V
LCDOUT
: LCD power supply
V
LCDSENSE
: voltage multiplier regulation input
(V
LCD
)
T1 to T12: test pads
SDAIN and SDAOUT: I
2
C-bus data lines
SCL: I
2
C-bus clock signal
SA0: slave address
OSC: oscillator
RES: reset
BLOCK DIAGRAM FUNCTIONS
Oscillator
I
2
C-bus interface
Display control logic
Display Data RAM (DDRAM)
Timing generator
LCD row and column drivers
INITIALIZATION
ADDRESSING
Display data RAM structure
RAM access
I
2
C-BUS INTERFACE
Characteristics of the I
2
C-bus
Bit transfer
START and STOP conditions
System configuration
Acknowledge
I
2
C-bus protocol
7.8
7.9
7.10
7.11
7.12
7.13
8
8.1
8.2
8.3
8.4
8.5
8.6
9
10
10.1
10.2
11
11.1
11.1.1
11.1.2
11.1.3
11.1.4
11.2
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.3
12.3.1
12.4
12.4.1
12.4.2
12.5
12.6
12.7
12.7.1
12.8
12.9
12.10
13
14
15
16
17
18
19
20
21
22
23
24
25
26
INSTRUCTIONS
External reset (RES)
Function set
Power-Down (PD)
V
H
MX
MY
Display control
D and E
Display configuration
TRS
BRS
Set Y address of RAM
Set X address of RAM
Set HV generator stages
S[1:0]
Temperature control
Bias system
Set V
OP
value
LIMITING VALUES
HANDLING
DC CHARACTERISTICS
AC CHARACTERISTICS
RESET
APPLICATION INFORMATION
CHIP INFORMATION
PAD INFORMATION
DEVICE PROTECTION DIAGRAM
TRAY INFORMATION
DEFINITIONS
LIFE SUPPORT APPLICATIONS
PURCHASE OF PHILIPS I
2
C COMPONENTS
BARE DIE DISCLAIMER
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