參數資料
型號： PCF8548
廠商： NXP Semiconductors N.V.
英文描述： 65 x 102 pixels matrix LCD driver
中文描述： 65 × 102像素矩陣LCD驅動器
文件頁數： 15/40頁
文件大?。?/td> 206K
代理商： PCF8548
1999 Aug 16
15
Philips Semiconductors
Product specification
65
×
102 pixels matrix LCD driver
PCF8548
11.2
I
2
C-bus protocol
The PCF8548 supports command, data write and status
read access.
Before any data is transmitted on the I
2
C-bus, the device
which should respond is addressed first. Two 7-bit slave
addresses (0111100 and 0111101) are reserved for the
PCF8548. The least significant bit of the slave address is
set by connecting the input SA0 to either logic 0 (V
SS1
) or
logic 1 (V
DD1
).
The I
2
C-bus protocol is illustrated in Fig.14.
The sequence is initiated with a START condition (S) from
the I
2
C-bus master which is followed by the slave address.
All slaves with the corresponding address acknowledge in
parallel, all the others will ignore the I
2
C-bus transfer. After
acknowledgement, one or more command words follow
which define the status of the addressed slaves.
A command word consists of a control byte, which defines
Co and D/C, plus a data byte (see Fig.14 and Table 1).
The last control byte is tagged with a cleared most
significant bit (i.e. the continuation bit Co). After a control
byte with a cleared Co bit, only data bytes will follow. The
state of the D/C bit defines whether the data byte is
interpreted as a command or as RAM data.
The control and data bytes are also acknowledged by all
addressed slaves on the bus.
Afterthelastcontrolbyte,dependingontheD/Cbitsetting,
either a series of display data bytes or command data
bytes may follow. If the D/C bit is set to logic 1, these
display bytes are stored in the display RAM at the address
specified by the data pointer. The data pointer is
automatically updated and the data is directed to the
intended PCF8548 device. If the D/C bit of the last control
byte is set to logic 0, these command bytes will be
decoded and the setting of the device will be changed
according to the received commands. The
acknowledgement after each byte is made only by the
addressed slave. At the end of the transmission the
I
2
C-bus master issues a STOP condition (P).
If the R/W bit is set to logic 1 the chip will output data
immediately after the slave address if the D/C bit, which
was sent during the last write access, is set to logic 0. If no
acknowledge is generated by the master after a byte, the
driver stops transferring data to the master.
Fig.14 I
2
C-bus protocol.
handbook, full pagewidth
MGS401
R/
W
S
A
0
S 0 1 1 1 1 0
S
A
0
0 A
acknowledgement
from PCF8548
acknowledgement
from PCF8548
acknowledgement
from PCF8548
acknowledgement
from PCF8548
acknowledgement
from PCF8548
1
control byte
A
data byte
data byte
n
≥
0 bytes
1 byte
slave address
command word
MSB . . . . . . . . . . . LSB
2n
≥
0 bytes
A
Co
Co
0
A
A P
DC
control byte
control byte
DC
S 0 1 1 1 1 0
S
A
0
1 A
acknowledgement
from PCF8548
acknowledgement
from master
PCF8548
slave address
status bytes
A
slave address
Read mode
Co
A
P
0 0 0 0 0 0
DC
1 1
0 1
1 0
相關PDF資料
PDF描述
PCF8549 65 x 102 pixels matrix LCD driver
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相關代理商/技術參數
參數描述
PCF8548U/2 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver
PCF8548U/9 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver
PCF8549 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver
PCF8549U 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver
PCF8549U/2 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:65 x 102 pixels matrix LCD driver
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