參數(shù)資料
型號(hào)： ORT8850H-1BM680C
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 85/105頁(yè)
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
80
This section describes device I/O signals to/from the embedded core.
Table 33. FPSC Embedded Core Function Pin Description (xx = AA, ..., BD)
Symbol
I/O
Description
HSI LVDS Receive Pins
RXDXX_W_P
I
Positive LVDS work link—Channel XX
RXDXX_W_N
I
Negative LVDS work link—Channel XX
RXDXX_P_P
I
Positive LVDS protect link—Channel XX
RXDXX_P_N
I
Negative LVDS protect link—Channel XX
DAUTREC
I
Disable auto recovery for the PLL. Internal pull-down.
VDDA_STM
I
Analog VDD 1.5 V power supply for the HSI block.
VSSA_STM*
I
Analog VSS for the HSI block.
HSI LVDS Transmit Pins
TXDXX_W_P
I
Positive LVDS work link—channel XX
TXDXX_W_N
I
Negative LVDS work link—channel XX
TXDXX_P_P
I
Positive LVDS protect link—channel XX
TXDXX_P_N
I
Negative LVDS protect link—channel XX
HSI Test Signals
TSTCLK
I
Test clock for emulation of 622 MHz clock during PLL bypass. Internal pull-
down.
MRESET
I
Test mode reset. Internal pull-down.
TESTRST
I
Resets receiver clock division counter. Internal pull-up.
RESETTX
I
Resets transmitter clock division counter. Internal pull-up.
TSTMUX[9:0]S
O
Test mode output port.
SCAN_TSTMD
I
Test mode enable. Must be tie-low for normal operation.
SCAN_EN
I
Scan test enable. Internal pull-up.
TSTSUFTLD
I
Internal pull-down.
E_TOGGLE
I
Internal pull-down.
ELSEL
I
Internal pull-down.
EXDNUP
I
Internal pull-down.
LVDS Interface Special Pins
LVCTAP_W[4:0]
—
LVDS work input center tap (use 0.01 F to GND).
LVCTAP_P[4:0]
—
LVDS protect input center tap (use 0.01 F to GND).
REF10
—
LVDS reference voltage: 1.0 V ± 3%.
REF14
—
LVDS reference voltage: 1.4 V ± 3%.
RESHI
—
LVDS resistor high pin ( 100
Ω in series with reslo).
RESLO
—
LVDS resistor low pin ( 100
Ω in series with reshi).
MISC System Signals
RST_N
I
Reset the core only. The FPGA logic is not reset by rst_n.
Internal pull down allows chip to stay in reset state when external driver loses
power.
SYS_CLK_P
I
Positive LVDS system clock, 50% duty cycle, also the reference clock of PLL.
SYS_CLK_N
I
Negative LVDS system clock, 50% duty cycle, also the reference clock of
PLL.
LVCTAP_SK
O
LVDS center-tap for SYS_CLK (use 0.01 f to GND).
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ORT8850H-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-2BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-2BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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