參數(shù)資料
型號： ORT8850H-1BM680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 70/105頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
67
30031*
30049
30061
30079
30091
300A9
300C1
300D9
[0:7]
enable elastic
store overow
ag 1, 4, 7, 10, 2,
5, 8, 11
00
Enable Bit for elastic store alarms. Set 1 to enable alarm
and propagate alarm to register 0x30026.
30032*
3004A
30062
3007A
30092
300AA
300C2
300DA
[0:6]
R
B1 parity error
counter
00
7 bit counter for the number of B1 parity errors in the
receive direction of the channel. Clear on read. Bit 6 is
MSB
[7]
R
B1 parity error
counter overow
0
Overow bit for B1 parity error counter
30033*
3004B
30063
3007B
30093
300AB
300C3
300DB
[0:6]
R
OOF counter
00
7 bit counter for the number of in-frame to OOF transitions.
Clear on read. Bit 6 is MSB
[7]
R
OOF counter
overow
0
Overow bit for OOF counter
30034*
3004C
30064
3007C
30094
300AC
300C4
300DC
[0:6]
R
A1 A2 frame
error counter
00
This counter increments when an errored frame pattern is
detected by the framer. Note that this is different from
OOF. In OOF state, you can detect the correct framing pat-
tern and still be out-of-frame.
[7]
R
A1, A2 error
counter overow
0
Overow bit for A1/A2 error counter
30035*
3004D
30065
3007D
30095
300AD
300C5
300DD
[0:4]
R
FIFO depth regis-
ter
30
Current value of the channel’s read address of the align-
ment FIFO. Bit 4 is the MSB
[5-7]
-
Not Used
0
30036*
3004E
30066
3007E
30096
300AE
300C6
300DE
[0:7]
R
Sampler phase
error counter
00
This is coming from the sampler block. The sampler looks
for bit transitions 0->1->0 to determine if the transitions
occur after 4 repeated bits. For e.g.: if you have
000011110000 then the 0->1->0 transition occurs in the
5th and 9th positions. It uses this to select one of the 4
repeated bits and form a repeated byte. When the transi-
tions happen at different bit positions, then the phase error
merely indicates that this has happened
Table 19. Memory Map Descriptions (Continued)
(0x)
Absolute
Address
Bit
Type
Name
Reset
Value
(0x)
Description
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參數(shù)描述
ORT8850H-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-2BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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