參數(shù)資料
型號： ORT8850H-1BM680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 43/105頁
文件大?。?/td> 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標準包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
42
Pointer Interpreter and Pointer Mover
After the alignment FIFO the receive data can optionally go through the pointer interpreter and pointer mover. The
pointer interpreter will identify the SONET payload envelope (SPE), the C1 bytes and the J1 bytes, and provide this
information to the FPGA logic. For data applications where the user is simply using SONET to carry user dened
cells in the payload the SPE signal is very useful as an enable to the cell processor. C1J1 for generic data applica-
tions can be ignored. If the pointer interpreter and pointer mover are bypassed, then the SPE and C1J1 signals will
be always '0'.
Since the start of an SPE can be located at any point in a SONET frame, the starting point is identied using
pointer bytes H1 and H2. The pointer bytes indicate the offset of the start of the SPE from the pointer byte position.
Two payload pointer bytes (H1 and H2) are allocated to a pointer that indicates the offset in bytes between the
pointer and the rst byte of the STS SPE. The pointer bytes are used in all STS-1s within an STS-N to align the
STS-1 Transport Overhead in the STS-N, and to perform frequency justication. These bytes are also used to indi-
cate concatenation, and to detect Alarm Indication Signals (AIS).
The resulting 2 byte pointer is divided into three parts:
1.
Four bits of New Data Flag (NDF)
2.
Two bits of unassigned bits (These bits are set to 00.)
3.
Ten bits for pointer value, which are alternately considered increment (I) bits or decrement (D) bits. The 10 bit
pointer is required to represent the maximum SPE offset of 782 (9 rows * 87 columns - 1). Specic combina-
tions of pointer byte values indicate that positive or negative frequency justication will occur and also whether
or not the current frame is a concatenated frame.
Normally the NDF bits are set to 0110, which indicates that the current pointer values are unchanged. The inverse
bit pattern, 1001, indicates that some data has changed. Any other bit conguration is interpreted using the 3 of 4
rule, i.e., 1110 is interpreted as 0110, etc. Patterns that cannot be resolved are undened, however all one's in the
NDF and in the pointer bits indicates AIS detection.The ORT8850 can correctly process any length of concatena-
tion of STS frames (multiple of three) as long as it begins on an STS-3 boundary (i.e., STS-1 number one, four,
seven, ten, etc.) and is contained within the smaller of STS-3, 12, or 48.
Table 13. Valid Starting Positions for and STS MC
STS-1
Number
STS-3cSPE
STS-6cSPE
STS-9cSPE
STS-12cSPE
STS-15cSPE
STS-18c to
STS-48c
SPEs
1
Yes
4
Yes
No
Yes
—
7
Yes
No
Yes
—
10
Yes
No
Yes
—
13
Yes
—
16
Yes
No
Yes
—
19
Yes
No
Yes
—
22
Yes
No
Yes
—
25
Yes
—
28
Yes
No
Yes
—
31
Yes
No
Yes
—
34
Yes
No
Yes
No
37
Yes
No
40
Yes
No
43
Yes
No
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ORT8850H-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-2BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-2BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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