參數(shù)資料
型號(hào)： ORT8850H-1BM680C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 56/105頁
文件大小： 0K
描述： IC FPSC TRANSCEIVER 8CH 680-BGA
產(chǎn)品變化通告： Product Discontinuation 01/Aug/2011
標(biāo)準(zhǔn)包裝： 24
系列： *
Lattice Semiconductor
ORCA ORT8850 Data Sheet
54
The next two examples show timing for serial TOH data input and output. For these cases, the clock is generated in
the FPGA logic and the discussion accounts for the skew between the clock signal at the FPGA latch and at the
FPGA/Core interface. The clock is routed over a secondary clock path and the skew can vary by ± 3 ns. A value of
+ 2 ns was assumed in the discussions.
Figure 30 shows the timing for sending serial TOH data from the Core to the FPGA logic with data being launched
and latched on the same (rising) clock edge. As in the previous examples, setup and hold time constraints for the
data versus the reference clock at the capturing latch must be met. Data is not captured before the next data is
launched, so there might be a hold time margin problem. Launched data has nearly a full clock period to become
stable at the capture latch and the maximum propagation delay is only 0.2 ns so setup margin should not be a
problem for the timing relationships assumed. Actual timing analysis should be performed for each application
because of the wide range of possible skew values.
Figure 30. Full Cycle, TOH Output Conguration and Timing (-1 Speed Grade)
D
+
Q
+
Δt
Embedded
Core
FPGA
Logic
Secondary Clock
0.4 ns
ASB_TOH_CLK
a. Configuration
b. Timing (ns)
FPGA_CLK
TOH_CLK
±3.0 ns skew
+2.0 ns assumed
TOH_CLK
0.0
4.7
9.4
14.1
18.8
ASB_TOH_CLK
0.4
5.1
8.8
14.5
19.2
Hold
Launch
FPGA_CLK
2.0
6.7
11.4
Capture
16.1
Data Valid
TOH_OUTxx
tprop_max = 2.0
tprop_min = - 0.5
Note: xx - [AA, AB, ..., BD]
TOH_OUTxx
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ORT8850H-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-2BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-2BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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